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 Solid state CMOS imager using silicon-on-insulator or bulk silicon

Details
Inventors: Dennard, Robert Heath; Wong, Hon-sum Philip;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Le; Que T.
Assistant Examiner:
Attorney, Agent or Firm: Trepp; Robert M.

An image sensor is described incorporating a plurality of detector cells arranged in an array where each detector cell has a MOSFET with a floating body and operable as a lateral bipolar transistor to amplify charge collected by the floating body. The invention overcomes the problem of insufficient charge being collected in detector cells formed on silicon-on-insulator (SOI) substrates due to silicon thickness and will also work in bulk silicon embodiments.

DETAILED DESCRIPTION Having thus described our invention, what we claim as new and desire to secure by Letters Patent is: 1.
An apparatus for detecting an image comprising: an array of detector cells for sensing radiant energy, an insulating substrate, a plurality of islands of single crystal semiconductor material over said substrate, at least one of said detector cells having a first, second, and third region adjacent one another formed in one of said islands, said second region positioned between said first and third regions wherein said first and third regions are doped to form a first type semiconductor material and said second region is doped to form a second type semiconductor material, a layer of insulation over said second region between said first and third regions to form a gate dielectric, and a gate electrode formed over said layer of insulation over said second region for holding charge in said second region during first times when radiant energy is being sensed, said second region positioned for receiving radiant energy to generate said charge in said second region, said first, second and third regions functioning as a lateral bipolar transistor at second times during readout in response to a control signal wherein said charge in said second region acting as a base of a bipolar transistor when in a bipolar mode flows to said first region acting as an emitter to provide current gain at said third region acting as a collector.
2.
The apparatus of claim 1 wherein said gate electrode is transmissive to radiant energy.
3.
The apparatus of claim 1 wherein said first type is n and said second type is p.
4.
The apparatus of claim 3 wherein said detector cells are arranged in rows and columns and further including circuitry for selecting one of said rows in response to address signals and a control signal for lowering the potential of the first region of respective detector cells in said row.
5.
The apparatus of claim 4 further including a column lead coupled to said third region of said detector cells in a column



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