Test structure for high precision analysis of a semiconductor

DETAILED DESCRIPTION The present invention is directed to a method and system for testing a semiconductor device involving the detection of parasitic capacitance to improve testing, designing, and debugging semiconductor chips.
The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor chip is analyzed.
A test structure having a device, at least one pad, and at least one metal lead connecting the pad to the device is formed in the chip.
A dummy structure is formed having a structure that is nearly identical to the test structure except for a gap in the metal lead to the device, wherein the gap disrupts the continuity to the structure.
The dummy structure is probed and the parasitic capacitance of the dummy structure is determined.
Using the determined parasitic capacitance to cancel out the parasitic capacitance of the test structure, the semiconductor chip is analyzed.
According to another example embodiment of the present invention, a system is arranged to test a semiconductor chip having a test structure and a dummy structure.
The system includes a first probe adapted to measure the parasitic capacitance of the dummy structure.
A second probe is adapted to couple to and analyze the test structure using the measured parasitic capacitance from the dummy structure.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention.
The figures and detailed description which follow more particularly exemplify these embodiments.