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Wafer level contact sheet and method of assembly
| Details |
Inventors: Budnaitis, John J.;
Assignee: W. L. Gore & Associates, Inc. (Newark, DE)
Primary Examiner: Niebling; John
Assistant Examiner: Lebentritt; Michael S.
Attorney, Agent or Firm: Genco, Jr.; Victor M.
The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use. |
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DETAILED DESCRIPTION The present invention relates to a system and method for performing reliability screening on semi-conductor wafers that uses a highly planar burn-in apparatus.
The burn-in apparatus includes a burn-in substrate unit with a high planarity base; a compliant, reusable, Z-axis member unit which can optionally include an elastomer; and a reusable Z-axis laminated wafer level contact sheet unit.
The burn-in substrate and wafer level contact sheet are electrically coupled to one another through the irregularly shaped conductive Z-axis pathways that extend through the thickness of the compliant, Z-axis member that is sandwiched therebetween.
The Z-axis pathways are electrically isolated from one another in the X and Y axes directions.
A test signal from the burn-in substrate is conveyed to the component being screened through bumps on the lower surface of the wafer level contact sheet that are registered and in contact with the component being screened.
Each bump at its upper end has a 4 to 8 mil pad and terminates in a tip that has a substantially planar configuration, and a surface diameter on the order of 0.
25 mils and 2 mil (about 8 .
mu.
m to 50 .
mu.
m), and preferably 0.
5 mils to 2 mil (about 12 .
mu.
m to 50 .
mu.
m).
Thus, the pad dimension to tip dimension ratio is between 2:1 to 32:1, preferably between 4:1 to 32:1.
The laminated wafer level contact sheet unit has an upper and lower surface and includes a plurality of uniformly configured conductive bumps on its lower surface alignable with and corresponding to contact pads of an integrated circuit or other electronic component.
The geometric configuration of the bump tip is sufficient to pierce an oxide layer that is formed on the contact pad of the semiconductor component.
The laminated contact sheet further includes a plurality of contact pads on its upper surface, each individually electrically connected to a corresponding conductive bump through an open cell, porous layer having selective Z-axis conductivity.
The base unit has balancing layers disposed on an upper portion thereof and circuitry layer on a lower portion thereof
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MEMS 
