Printed circuit board design utilizing flexible interconnects for programmable logic components

DETAILED DESCRIPTION Although this invention is susceptible to embodiments of many different forms, a preferred embodiment will be described and illustrated in detail herein.
The present disclosure exemplifies the principles of the invention and is not to be considered a limit to the broader aspects of the invention to the particular embodiment as described.
FIG.
1 illustrates a typical circuit board assembly 1 with various components mounted on a printed circuit board 2.
The circuit board 2 could be double sided or multilayered.
A microprocessor 4 is supported by memory chips 6 and 8 and clock 10.
A field programmable gate array (FPGA) 12 provides most of the digital logic and means for driving and decoding a data bus and an address bus and for interfacing with input and output devices which are assessable through edge conductors 14 and a multipin connector 16.
A field bus connector 18 is interfaced with an asynchronous communication interface adapter 20 which is coupled to the FPGA 12 to send and receive data over a bus network.
Another communications port 22 is coupled to UART 24 for serial communications.
The circuit board assembly 1 may also contain a display 26 with drivers 28 and programming switches S1, S2, and S3.
Not shown are various peripheral chips.
Given the complexity of all the components and interconnections shown, the design of the printed circuit board 2 is a major undertaking.
Referring to FIG.
2 and 2A, an outline drawing of a FPGA 30 having 160 pins 32 is shown.
This device is mounted to a printed circuit board using surface mounting technology.
The placement of a chip of this size has a large impact on the design of the printed circuit board 2.
Many of the pins 32 have fixed assignments such as power inputs, reset lines, clock signals, enables, and so on.
However, since the functionality of the FPGA 30 is programmable, the pinout of input and output signals can vary considerably.
Whereas this allows for ease of change within the FPGA 30, the device is usually soldered to fixed conductive patterns on the printed circuit board 2