CMOS shift register with complementary refresh pass gates and buffer

DETAILED DESCRIPTION FIG.
1 is a circuit diagram of a CMOS shift register constructed in accordance with prior technology.
The shift register includes pass gates 14, 18, 22 and 26, inverters 15, 19, 23 and 27 for holding passed bit values and various refresh inverters and transistors for refreshing the held values.
The shift register also requires clock generating and clock compensating circuitry, as discussed below.
Pass gates 14 and 18 and the associated holding and refresh circuitry form one cell and pass gates 22 and 26 and the associated holding and refresh circuitry form a second cell.
A master clock (generator not shown) provides to the shift register a master clock signal, .
phi.
.
From this master clock signal, .
phi.
, the clock generating circuitry, 10-12 generates the two required clock signals, namely, clock signal, .
phi.
.
sub.
c, and complementary clock signal, .
phi.
.
sub.
cc.
The clock generating circuitry 10-12 must delay the clock signal, .
phi.
.
sub.
c, such that it is 180.
degree.
out of phase with the complementary clock signal, .
phi.
.
sub.
cc.
Thus the delay of inverter 10 must be precisely matched to the combined delay of the inverters 11 and 12.
When the clock signal, .
phi.
.
sub.
c, is low, gate 14 conducts, that is, PMOS transistor 14P which is driven by the low clock signal, .
phi.
.
sub.
c, and NMOS transistor 14N which is driven by the high clock signal, .
phi.
.
sub.
cc, turn on.
The gate thus passes the bit value A into the first cell, to inverter 15.
The bit value A is "written" in the cell when the inverter 15 latches to its output port the inverse of the passed value, or "inverse A.
" The inverter 15 then holds the inverse of the passed value while gate 18 conducts and passes the bit value out of the cell.
The output signal from inverter 15, that is, inverse A, becomes the input signal for refresh, or feedback, inverter 17.
When the feedback pass gate 16 turns on, it passes to the input of inverter 15 the output signal of the feedback inverter 17.
Thus it passes the value A to the inverter