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Current mirror arrays
| Details |
Inventors: Schneider, Herbert A.;
Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ)
Primary Examiner: Pellinen; A. D.
Assistant Examiner:
Attorney, Agent or Firm: Phelan; Charles Scott, Stafford; Thomas
Improved current sources which provide n output units of current responsive to m input units of current are constructed by connecting (m+n).sup.2 transistors in a square array configuration, controlled by (m+n) control devices. The array contains (m+n) columns each of which conducts a current the magnitude of which is desired to equal the magnitude of the current flowing in every other column, and has a maximum deviation only in proportion to [1/(1+.beta.)].sup.4 where .beta. is the common emitter current gain of the transistors. |
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DETAILED DESCRIPTION A multiplying current mirror array which controls two units of output current (n=2) with one unit of input current (m=1) is schematically illustrated in FIG. 1. Current mirrors 110, 120 and 130 are each comprised of four PNP transistors, three of which are provided base drive current by the fourth transistor. Referring to current mirror 120 which is representative of the structure and operation of remaining current mirrors 110 and 130, controlled transistors 121, 122 and 123 are arranged as a row of the array and have their bases connected to each other. Each controlled transistor is supplied current at its emitter terminal from the collector of a corresponding controlled transistor in current mirror 110 and in the same column. The three controlled transistors in current mirror 120 are each provided base current control by control transistor 124 which has its emitter connected to the bases of the controlled transistors, its collector grounded and its base connected to the collector of controlled transistor 122. In the same current mirror, I. sub. 30 is the input current and I. sub. 21 and I. sub. 22 are output currents. As indicated, current mirrors 110, 120 and 130 are functionally identical and contain corresponding elements of structure. The current mirrors are connected to each other in a cascode configuration so as to form, in this embodiment of the invention, three columns of serially connected controlled transistors. The columns are identified at the top of the circuit schematic as COLUMN 1, COLUMN 2, and COLUMN 3, and are each connected to a common terminal 101 for receiving an energizing potential. COLUMN 1 is comprised of serial controlled transistors 111, 121 and 131 in current mirrors 110, 120 and 130 respectively. Current is conducted from a source of potential +V connected at terminal 101 through the controlled transistors and through current control means 151, which is connected between input current terminal 141 and ground. The current control means in the function block identified as 151 contains any circuitry known in the art which can control the magnitude of current I
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