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| On-line oil-in-wax monitoring apparatus and method |
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| Magnetometer having coil formed by two spiral shaped conductors |
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| Magnetic recording head motion translation apparatus for head/media evaluation systems |
| OF THE PREFERRED EMBODIMENT In reference to FIG. 1 of the drawing, there is shown a partially-... |
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| Air bladder apparatus for positioning a magnetic head |
| I claim: 1. A magnetic head load-unload device for use with an actuator in the recording and ... |
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| Electric generator that operates with few ampere-turns in field winding |
| OF PREFERRED EMBODIMENTS Referring particularly to FIGS. 1 and 2, the numeral 20 generally denotes ... |
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| AC Generator with low noise claw tooth rotor |
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High voltage tolerant CMOS input/output pad circuits
| Details |
Inventors: Motley, Gordon W.; Meier, Peter J.; Maitland, David S.;
Assignee: Hewlett-Packard Company (Palo Alto, CA)
Primary Examiner: Gaffin; Jeffrey A.
Assistant Examiner: Medley; Sally C.
Attorney, Agent or Firm:
A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage. |
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DETAILED DESCRIPTION OF THE INVENTION The drawing, in general, depicts high voltage tolerant CMOS input/output pad circuits in accordance with the present invention, and for use in applications requiring high voltage tolerant input/output pads.
A high voltage tolerant CMOS output driver circuit 100 is shown in FIG.
1, with an enhanced embodiment shown in FIG.
2, and a high voltage tolerant CMOS input receiver circuit 200 is shown in FIG.
3.
1.
Output Driver Turning now in detail to the drawing, FIG.
1 depicts a high voltage tolerant CMOS output driver circuit 100 in accordance with the present invention.
As will be described in detail hereinafter, the high voltage tolerant CMOS output driver circuit 100 of FIG.
1 provides the functionality for driving an output pad to one of three states; namely, low, high and inactive (tri-state).
The functionality of the high voltage tolerant CMOS output driver circuit 100 may be divided into three functional stages: low stage S1, high stage S2 and tri-state stage S3.
Low stage S1 includes a first data input node N13 coupled to the input 30 of an inverter 2.
In the preferred embodiment, inverter 2 is implemented using a complementary symmetry inverter, shown in FIG.
2, comprising a PFET device M15 and an NFET device M16.
The output 31 of inverter 2 is coupled at node N12 to the gate 32 of a first NFET device M5.
The first NFET device M5 has a source 34 coupled to ground and a drain 33 coupled at node N10 to the source 37 of a second NFET device M4.
A supply voltage V.
sub.
DD is coupled to the gate 35 of the second NFET device M4.
The drain 36 of the second NFET device M4 is coupled to a pad node N7.
High stage S2 includes a second data input node N1 coupled to the input 10 of an inverter 1.
In the preferred embodiment, inverter 1 is implemented using a complementary symmetry inverter, shown in FIG.
2, comprising a PFET device M13 and an NFET device M14.
The output 11 of inverter 1 is coupled at node N2 to the gate 12 of a first PFET device M3.
The second data input node N1 is also coupled to the gate 16 of a third NFET device M9
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Metal Working 
