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Image blanking circuit for line follower
| Details |
Inventors: Kallen, George H.;
Assignee: Union Carbide Corporation (Danbury, CT)
Primary Examiner: Nelms; David C.
Assistant Examiner: Hostetter; Darwin R.
Attorney, Agent or Firm: Lieberstein; Eugene
A window generation circuit is provided for gating image signals from an electronically scanned sensor array in a line tracing machine. The window generation circuit includes two shift registers of variable length for measuring intervals of time for setting first and second bounds to a sector scan. The interval of the second register corresponds to the width of the window. Logic circuitry, responsive to the detection of image data, alters the electrical lengths of the registers to enlarge the window in the absence of an image, and restores the original lengths upon return of the image. |
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DETAILED DESCRIPTION The aforementioned problem is overcome and other advantages are provided by a window generation circuit adapted for use with scanned arrays of detectors.
As used herein, the term "window" is understood to refer to an interval of time, and a corresponding portion of the aforementioned scan, during which image data is admitted to a scanning system.
The window is said to be open when signals conveying such data are admitted to the scanning system.
The window is said to be closed when signals conveying such data are excluded from the scanning system, as by use of a gating or blanking circuit.
The operation of the window generation circuit is synchronized with the scanning system so that specific points of an image can be received or blanked during a scan of an array of photodetectors.
Synchronization of the operation of the window generation circuit and the scanning system is accomplished by use of a common time base.
While the window generation circuit may be utilized in a variety of applications wherein it is required to receive certain signals while blanking other signals, the preferred embodiment of the invention has been implemented in conjunction with a line edge follower constructed substantially such as that of the foregoing U.
S.
Pat.
No.
4,049,962.
As disclosed therein, a phase locked frequency multiplier circuit is utilized for producing timing, or clock, pulses at a rate much higher than the rate at which the array is scanned.
For example, where the array contains 64 photodiodes, the clock rate is 64 times the rate at which the circular array is scanned.
The clock rate is used for extracting data from individual ones of the photodiodes and, furthermore in accordance with the invention, is used for operating the window generation circuit in synchronism with the scanning operation.
In accordance with the invention, the window generation circuit comprises a plurality of serially connected shift registers, each of which may be of electronically variable lengths.
Two such registers are utilized in the preferred embodiment of the invention with an output terminal of a first one of the registers being coupled to an input terminal of the second of the registers
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Metal Working 
