 Apparatus for preventing the twisting of an electrical cord or cable |
| OF THE FIGURES Referring to FIG. 1, there is shown the device 10 which apparatus or device has an ... |
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| Electrical connector |
| It is an object of the present invention to provide an electrical connector which eliminates the ... |
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| Manual crimping pliers |
| I claim: 1. Manual crimping pliers for connecting contact elements to electrical conductors, the ... |
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| Electric switch and actuator for an antenna drive system |
| The embodiments of the invention in which an exclusive property or priviledge is claimed are ... |
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| Reclining seat particularly for vehicles |
| I claim: 1. A seat comprising: a cushion portion and a back portion pivotally connected thereto; a ... |
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| Gear mechanism for brake adjustment |
| OF THE ILLUSTRATED EMBODIMENT An adjustable brake operating mechanism constructed in accordance ... |
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| Tapered worm |
| The invention is claimed as follows: 1. A worm and a gear meshing therewith, said worm comprising a ... |
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| Double enveloping worm and gear seat recliner |
| The present invention provides an improved reclining seat back drive mechanism addressing the ... |
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| Method of manufacturing an electric discharge tube |
| What is claimed is: 1. A method of manufacturing an electric discharge tube of the type having, in ... |
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| Locking fuel cap |
| The embodiments of the invention in which an exclusive property or privilege is claimed are defined ... |
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Method of making a single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization
| Details |
Inventors: Hsu, Sheng Teng; Lee, Jong Jan;
Assignee: Sharp Laboratories of America, Inc. (Camas, WA); SharpKabushiki Kaisha (Osaka, JP)
Primary Examiner: Tsai; Jey
Assistant Examiner:
Attorney, Agent or Firm: Ripma; David C., Rabdau; Matthew D.
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of the first type in the conductive channel well of the second type to form a conductive channel of the first conductivity type for use as a gate junction region, implanting doping impurities of the second type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of the second conductivity type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of the first conductive type formed in the second conductivity type well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, doped to form conductive channels of second conductive type. A FEM gate unit overlays the conductive channel of the gate junction region. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The ferroelectric memory (FEM) cell of the invention may be formed on a SOI (SIMOX) substrate, or, it may be formed in a bulk silicon substrate.
The description herein will concentrate on the formation of the FEM gate unit on a bulk silicon substrate.
Turning now to FIG.
1, a silicon substrate is depicted at 10.
Substrate 10, in the preferred embodiment is a single-crystal substrate, and is formed of bulk silicon.
Other embodiments may be formed on a SOI substrate.
As used herein, "silicon substrate" refers to either a bulk silicon substrate or a SOI substrate, or to any other suitable silicon-based substrate.
As depicted in FIG.
1, the p.
sup.
- substrate 10 has doping impurities of a first type, which is a boron or boron compound, of a concentration of about 1.
0.
multidot.
10.
sup.
15 cm.
sup.
-3 to 5.
0.
multidot.
10.
sup.
15 cm.
sup.
-3.
A shallow n.
sup.
- type layer 12, also referred to herein as conductive channel of a second type, which has doping impurities of a second conductivity type, is then formed under the gate area by phosphorous or arsenic implantation.
The ion energy is in the range of 10 keV to 50 keV and the dose is in the range of 1.
0.
multidot.
10.
sup.
12 cm.
sup.
-2 to 1.
0.
multidot.
10.
sup.
13 cm.
sup.
-2.
A very shallow layer of p.
sup.
- type silicon 14 is formed, and has doping impurities of a third type, which are the same as the doping impurities of the first type, implanted with BF.
sub.
2 to the top of the n.
sup.
- type second conducting layer.
The BF.
sub.
2 energy is in the range of 10 keV to 40 keV, and the dose range is between about 5.
0.
multidot.
10.
sup.
11 cm.
sup.
-2 to 5.
0.
multidot.
10.
sup.
12 cm.
sup.
-2.
This layer is referred to herein as a conductive channel of a first conductivity type in the conductive channel of the second conductivity type for use as a gate junction region.
At this point, formation of the FEM gate unit may begin.
A FEM gate unit is identified generally at 16.
and includes a lower metal layer, or electrode, 18, the ferroelectric (FE) material 20 and a upper metal layer, or electrode, 22
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Metal Working 
