Semi-monolithic memory with high-density cell configurations

DETAILED DESCRIPTION In this invention, a floating cell memory structure provides a novel means of constructing dynamic random access memories (DRAMs) for applications such as computers.
The floating cell memory structure is designed to gain special benefits from an inventive semi-monolithic integration (SMI) fabrication method when this method is used with inventive excise and bypass yield enhancement techniques.
A floating cell dynamic memory comprises repetitions of memory cells which are normally isolated (floating) from any circuit ground or B+ voltage source, unlike memory cells in conventional dynamic random access memories.
Each of these cells comprises a capacitor and two diodes.
For reading, writing or refreshing, individual cells are temporarily accessed by electronically switching them into drive or sense circuits.
Switched connection occurs at the ends of pairs of nominally horizontal temporarily active circuit interconnection rows, which correspond to bit lines in a field effect transistor DRAM.
One row in a pair is used for writing, and the other row in a pair is used for reading.
Single nominally vertical temporarily active circuit interconnection columns are used in conjunction with these row pairs for both reading and writing.
These columns correspond to word lines in a field effect transistor DRAM.
A floating cell memory is preferably constructed with a small number of columns and a large number of rows to allow control of reverse current feedback, and also to facilitate the subsequently described method of semi-monolithic integration.
A limited number of reverse current isolating diodes are inserted at regular intervals along the rows, after which a booster amplifier (such as a field effect transistor circuit) is added to increase signal strength.
The intervening booster amplifiers preferably are located on separate integrated circuit dice which are interconnected by the subsequently described semi-monolithic integration method.
The semi-monolithic integration (SMI) technology used to fabricate this memory is a new method for cutting apart individual monolithic integrated circuit dice, and then reconnecting them on a specially designed silicon substrate