ASIC cell implementation of a bus controller with programmable timing value registers for the apple desktop bus

DETAILED DESCRIPTION An ASIC cell implementation of an ADB bus controller for the Apple Desktop Bus has a system interface for connecting to a computer system, and an ADB Interface for connecting to an Apple Desktop Bus.
The system interface connects the ASIC cell ADB bus controller to an attached computer system, which can include connecting the ADB bus controller to other elements on the ASIC chip, connecting the ADB bus controller to a bus which connects to other elements on a motherboard, such as a central processing unit (CPU), or connecting the ADB bus controller to a bus which connects between computer system boards, such as a PCI bus.
In one form, the system interface includes an address bus interface, a data bus interface and a control bus interface for connecting to corresponding computer system busses.
Within the ASIC cell ADB bus controller are a command/data register, programmable timing value registers, and a control state machine.
The command/data register is used for temporarily holding data within the ADB bus controller and for transferring data to the computer system via the system interface and to the Apple Desktop Bus via the ADB interface.
The programmable timing value registers store timing data which is loaded from the attached computer system.
The control state machine uses the stored timing data to implement the Apple Desktop Bus data signaling and communications protocol on the ADB interface.
An ADB bus controller in accordance with this invention allows the timing data stored in the timing value registers to be easily changed, thereby accommodating different ADB devices or changes in the ADB protocol.
Because the timing data and the control state machine needed to implement ADB signaling are within the ADB bus controller, the ADB bus controller can implement ADB signaling on the ADB interface without interaction with the attached computer system.