Arithmetic and logic computation device and control method

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment (by way of example, and not of limitation), in which: The arithmetic and logic computation device shown in FIG.
1 has a control unit UC to drive the different circuits of the computation device, notably an arithmetic and logic unit ALU and a multiplier MULT.
The control unit receives an instruction INS, for example, from an instruction bus IBUS (using the standard architecture of signal processors known as the HARVARD architecture).
It delivers different control signals (m0, .
.
.
, m4) as a function of this instruction.
The arithmetic and logic unit is capable of carrying out standard arithmetic and logic instructions (addition, subtraction, XOR, comparison, etc.
).
It has at least two data inputs E1 and E2.
On at least one input, for example in the input E1 (FIG.
1), a shifter BD is provided.
Preferably, it is a barrel shifter that enables arithmetic and logic shifts.
An arithmetic and logic unit delivers a result at an output OUT preferably associated with at least two output registers A0 and A1 called accumulators.
These accumulators may also give data elements to the inputs E1 and E2 of the arithmetic and logic unit.
A first register C1 and a second register C2 are designed to memorize and give the carry computed by the arithmetic and logic unit.
A circuit 1, controlled by the control unit UC, enables the selection of that one of the two registers C1 or C2 that memorizes and gives the carry for the operation in progress.
In fact, at the start of the computation, the selective register gives the arithmetic and logic unit the carry that it has memorized.
At the end of the computation, it memorizes the new carry.
The register selected by default is the register C1.
Preferably, the circuit 1 has a multiplexer/demultiplexer receiving firstly the carry signal of the arithmetic and logic unit and, secondly, on a first channel, the output of the register C1 and, on a second channel, the output of the register C2