Arrangement for converting binary input signal into corresponding in-phase and quadrature phase signals

DETAILED DESCRIPTION It is an object of the present invention to provide an arrangement which features an effective reduction of memory size required for each of the ROM(s) provided therein.
In brief, the above object is achieved by an arrangement which includes a memory output controller and a sequential logic.
The arrangement is able to effectively reduce a memory size of each of two memories provided in an arrangement for converting a binary input data into the corresponding in-phase and quadrature signals.
The memory output controller includes two polarity control circuits and two input data selectors.
The two polarity control circuits are respectively coupled to the two memories, while the two input data selectors are preceded by and coupled to both of the two polarity control circuits.
Each of the two polarity control circuits reverses the polarity of the output of the associated memory according to the output of the sequential logic.
On the other hand, each of the two input data selectors is arranged to selectively acquire the outputs of the two polarity control circuits depending on the output of the sequential logic.
More specifically an aspect of the present invention is an arrangement for converting binary input data into corresponding in-phase and quadrature signals, having: a counter for receiving a first clock signal and counting clock pulses of the first clock signal up to N (N is a natural number).
The counter generates a plurality of counter outputs at a given time point.
A shift register including a plurality of shift stages from which shifted data are derived is provided, the shift register acquiring the binary input data and shifting the same in response to a second clock signal the frequency of which is 1/N of the first clock signal.
A first memory section for pre-storing a look-up table including cosine data and receiving an address signal which consists of first bit signals each derived from the shift stages and second bit signals each derived as the counter output from the counter is also provided, the first memory section producing an output defined by the address