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| Method and apparatus for CT image registration |
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| CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration |
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Batch fabricated semiconductor micro-switch
| Details |
Inventors: Miu, Denny K.; Clymer, James R. W.; Endter, Paul A.; Temesvary, Viktoria A.; Hsu, Tseng-Yang; Tang, Weilong;
Assignee: Integrated Micromachines, Inc. (Burbank, CA)
Primary Examiner: Whitehead, Jr.; Carl W.
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel LLP, Klivans; Norman R.
A micro-switch having a flexible conductive membrane which is moved by an external force, such as pressure from an air flow, to establish a connection between contact pads. The conductive membrane is stretched over one or more spacer pads to introduce deformation in the conductive membrane, thereby improving the accuracy and repeatability of the micro-switch. The spacing between the contact pads and the conductive membrane is precisely controlled by controlling the height difference between the spacer pads and the conductive pads. This height difference is determined by one or more precisely controlled etch operations. |
|
DETAILED DESCRIPTION FIG.
1 is a top view of a lower structural member 101 of a micro-switch 1 in accordance with one embodiment of the present invention.
As described in more detail below, the lower structural member 101 is joined to an upper structural member 201 (FIGS.
4, 5) to form the micro-switch 1 (FIG.
6).
FIG.
2 is a cross sectional view of the lower structural member 101 along section line 2--2 of FIG.
1.
FIGS.
1 and 2 use the illustrated X-Y-Z coordinate system.
Lower structural member 101 includes a substrate 102, a plurality of holes 105 which extend through the substrate 102, a circular pattern of spacer pads 131 (including spacer pads 131A and 131B), a pattern of support pads 132 (including support pads 132A-132F), contact pads 151-153, conductive traces 141-143, and bond pads 161-163.
In the described embodiment, substrate 102 is a monocrystalline silicon wafer having a <100> crystalline structure.
In this embodiment, substrate 102 has a thickness along the Z-axis in the range of 400 to 700 .
mu.
m.
In other embodiments, other structural materials can be used to form substrate 102.
An array of trapezoidal holes 105 are formed through substrate 102 at a centrally located region of substrate 102.
In the described embodiment, there are eight holes 105, each of the holes 105 having an area of approximately 100.
times.
100 .
mu.
m at the upper surface 102A of the substrate 102.
The holes 105 are provided to vent to the atmospheric pressure or another air chamber through substrate 102.
A patterned cavity 114 is formed in the upper surface 102A of the substrate 102.
In the described embodiment, the depth of cavity 114 is approximately 5 .
mu.
m along the Z-axis.
The cavity 114 defines the locations of the spacer pads 131, the support pads 132, and the contact pads 151-153.
The functionality of cavity 114 will become apparent in view of the subsequent disclosure.
A patterned insulating layer 121 is located over the upper surface 102A of the substrate 102.
The patterned insulating layer 121 has a varying thickness along the upper surface 102A of the substrate 102
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