Binary coded decimal addressed Read-Only-Memory

Details

Inventors: Someshwar, Ashok H.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Shaw; Gareth D.
Assistant Examiner: Heckler; Thomas M.
Attorney, Agent or Firm: McCord; William K., Comfort; James T., Sharp; Melvin

A Read-Only-Memory (ROM) is addressed with a binary coded decimal (BCD) address in an address register or program counter. The ROM comprises an array of memory cells with associated row and column lines for addressing the array. Row and column decoders responsive to the address in the address register identify a unique row and column line for each BCD address. The row and column decoders comprise a plurality of decoders in cascaded levels. The decorders in any given level decode particular bits of the address in the address register; these decoders decode a one-out-of-a-prime-number, which prime number is a factor of the number of memory locations in the array.

DETAILED DESCRIPTION An electronic calculator system having high order capability, which uses the present invention, will be described with reference to two U.
S.
Patents or applications.
Line 21, column 4 through line 31, column 44 of U.
S.
Pat.
No.
3,900,722 and the entirety of U.
S.
Patent application Ser.
No.
783,903 is incorporated herein by reference.
For a complete understanding of the calculator system employing the present invention, as well as definitions and explanations of the control and timing signal referred to herein, reference should be made to the aforementioned U.
S.
Patents.
It should be appreciated that the following is a detailed description of one chip, used in a multi-chip calculator system and a description of other chips preferably used with the chip herein discribed is contained in the aforementioned U.
S.
Patents.
The Read-Only-Memory (ROM) disposed on this chip is called the second ROM and it is used to store a plurality of program codes, each program code being effective for addressing a set of instruction words stored in a main program ROM (and referred to as a first ROM).
Inasmuch as the address used to address the second ROM may be altered by a relative amount with appropriate keyboard inputs and since the keyboard includes a decimal number keyboard, the second ROM is addressed by a BCD address in an address register.
The address register is, in this embodiment a shift register and add one/BCD corrector circuit is included to increment the address in the address register in response to a control signal.
A decoded FETCH instruction supplies this control signal in this embodiment.
The tables referred to herein are hereby incorporated by reference to the aforementioned U.
S.
Patent application Ser.
No.
783,903.
DESCRIPTION OF THE SECOND ROM CHIP AND THE INTERFACE BETWEEN THE SECOND ROM CHIP AND THE OTHER CALCULATOR CHIPS Referring now to FIG.
17, there is shown a block diagram of second ROM chip 48'.
The second ROM 48 implemented thereon, is provided by binary coded decimal (BCD) ROM 600

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