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Cell signal processing circuit and optical switch apparatus using the same
| Details |
Inventors: Takahashi, Yasushi; Amada, Eiichi; Ando, Kimiaki; Miyata, Masanori;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Gregory; Bernarr E.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus
A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of a signal adder circuit for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit for separating and outputting the time series cell signals. Each dummy signal being composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the cell signal processing circuit as an optical switch array is also provided which includes a photoelectric converter for converting the time series optical cell signal to an electric signal, a clock recovery circuit for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit for deciding between signals in the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention is simple and is not influenced by data loss and jitter. |
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DETAILED DESCRIPTION It is a principal object of the present invention to provide a cell signal processing circuit which is capable of precisely extracting a timing signal and a cell synchronizing signal and an optical switch apparatus using the same.
To achieve the above object, the present invention provides a cell signal processing circuit which processes input signals in a cell form, wherein means for adding a unique signal pattern including the same number of bits "0" and bits "1", that is, a direct current balanced signal (also referred to as a dummy signal) to each cell of input signals is provided in an input section thereof, such that the cell signal processing circuit drives the optical switch at a time of a bit sequence of "0"s included in the unique signal pattern.
Also, an optical switch apparatus is composed of the above signal processing circuits as an optical switch array and also comprises means for detecting the particular signal for reproducing a cell synchronizing signal at an output section of the optical switch apparatus and means for generating the cell synchronizing signal by the use of an output from the detecting means.
The dummy signal is in a direct current balanced state, that is, it exhibits a mark density of 0.
5.
Also, since an input signal cell is generally scrambled, such scrambled part as well as the entire input signal cell exhibit a mark density of 0.
5.
Thus, there is substantially no direct component, whereby any problem will be incurred even if a decision circuit is alternate current coupled.
Since the optical switch array is changed over at a time of a "0" bit pattern in the added dummy signal, an optical signal level at a transition is zero, whereby a temporary data loss due to a transition, even if produced, neither a change in the mark ratio nor an increase in signal level changing points will arise.
Since unnecessary signal level changing points are not increased, it is possible to prevent the clock reproducing circuit from malfunctioning, which renders it possible to employ an ordinary optical receiver on the output port side
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Multiplexer-related 
