Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock

DETAILED DESCRIPTION The present invention is made in view of the aforementioned problems and accordingly an object of the present invention is to provide a recording-reproducing clock generator circuit enabled to make a stable startup.
Another object of the present invention is to keep the relative phase from being shifted by change in temperature or the like and to enable the clock to be generated correctly.
A further object of the present invention is to provide a phase comparator circuit capable of phase comparison of a single having only single edge information.
A still further object of the present invention is to provide a synchronizing signal detector capable of detecting the synchronizing signal accurately even if defects or the like are present.
The recording-reproducing clock generator circuit of the present invention is adapted to generate a reference clock having a predetermined frequency, generate a first sync signal detection signal when the value of the distance, measured in the clock pulses, between two successive pulses in the input signal is equal to a predetermined reference value, output a clock edge pulse separated from the input signal by using the first sync signal detection signal, and generate a reproduced clock having a predetermined frequency whose generation timing is synchronized with the separated clock edge pulse.
According to a second feature of the present invention, a PLL circuit including a phase comparator circuit for comparing phases of clock data and a clock whose frequency is different from that of the clock data is supplied with a signal corresponding to the pulse spacing of the clock data.
Specifically, the clock generator circuit according to the second feature of the present invention comprises a PLL circuit consisting of a phase comparator circuit for comparing phases of clock data and a clock at a frequency different from that of the clock data, a low-pass filter for smoothing the output of the phase comparator circuit, and a voltage-controlled oscillator circuit controlled in response to the output of the low-pass filter for generating the clock a counter detecting the pulse spacing of the clock data or a signal synchronized with the clock data by counting the clock pulses, and a supply circuit for supplying the PLL circuit with a signal corresponding to the count value of the counter