Clock signal extracting circuit

DETAILED DESCRIPTION It is accordingly an object of the present invention to provide a clock signal extracting circuit which can eliminate the drawbacks of conventional circuits, which is economical and can be made small in size, and whose characteristic is not degraded.
In order to attain the above object, according to an aspect of the present invention, there is provided a clock signal extracting circuit in which an input data signal is sampled and held in accordance with a predetermined sampling frequency to produce a discrete signal having a steplike waveform, the discrete signal thus obtained is subjected to equalization and amplification, a difference in amplitude is detected between those portions of the steplike discrete signal which appear on both sides of the steplike portion of the discrete signal corresponding to the maximum amplitude of the input data signal, the sampling frequency is controlled by the detected amplitude difference so that the amplitude difference is equal to zero thereby to determine a phase at which the input data signal has a maximum amplitude, and a clock signal phase-synchronized with the determined phase is extracted and reproduced from the steplike waveform obtained after the equalization and amplification.