Code converting method and system

DETAILED DESCRIPTION What we claim is: 1.
A code converting system in which a multivalue signal x.
sub.
1 (x.
sub.
1 being non-negative integer not greater than m being even number) of a sampling period mT is received and subjected to density conversion to be delivered out in the form of a train of m binary signals of a sampling period T, the system comprising a holding circuit for holding said multivalue signal x.
sub.
1 at the period mT, logic means connected to said holding circuit serving to invert the output state of said logic means when said multivalue signal assumes an odd number, and operation means receiving the output of the holding circuit and said output q.
sub.
i (q.
sub.
i being 1(one) or zero) of the inverting means and delivering out a Z-transform .
beta.
(Z) of the binary signals to be delivered out, said Z-transform being expressed as, ##EQU15## where H(x.
sub.
i,q.
sub.
i,Z) represents a polynomial of the order related to Z.
sup.
-1 less than (m-1) which has non-zero terms having each a coefficient of 1(one) and which satisfies H(k,q.
sub.
i,1)==k, H(k,q.
sub.
i,Z)=Z.
sup.
-(m-1) H(k,q.
sub.
i,(1/Z) for k being even number, and H(k,0,Z)=Z.
sup.
-(m-1) H(k,1,1/Z) for k being an odd number.
2.
A code converting system according to claim 1, wherein the output q.
sub.
i satisfies q.
sub.
o =0 q.
sub.
i+1 =q.
sub.
i +x.
sub.
i+1 +m, mod 2 3.
A code converting system according to claim 2, wherein the H(x.
sub.
i,q.
sub.
i,Z) satisfies H(k,0,Z)=H(k,1,Z) for k being an even number.
4.
A code converting system according to claim 3, wherein m represents m=2.
sup.
n (n being an integer).
5.
A code converting system in which a multivalue signal x.
sub.
i (x.
sub.
i being non-negative integer not greater than m being even number) of a sampling period mT is received and subjected to density conversion to be delivered out in the form of a train of m binary signals of a sampling period T, the system comprising: input terminals for receiving binary signals corresponding to said multivalue signal x.
sub.
i ; a multi-bit holding circuit connected with said input terminals for holding said binary signals for a time period of mT; a logic circuit connected so as to be fed with the least significant bit output of said holding circuit, said logic circuit serving to invert its output q