Computer system with PCI repeater between primary bus and second bus

DETAILED DESCRIPTION A computer system of the present invention includes a PCI bridge or repeater to increase the number of capacitive loads on a PCI bus without requiring significant changes to software.
The PCI repeater connects a primary portion of the PCI bus to a secondary portion of the PCI bus.
The portions act as one logical bus but are electrically separate for loading purposes.
An arbiter controls access to the buses.
Transactions initiated on the primary bus and intended for a target on the secondary bus are downstream transactions.
Transactions initiated on the secondary bus and intended for a target on the primary bus are upstream transactions.
Transactions initiated on the primary bus are echoed, passed or reflected to the secondary bus, and vice versa.
Signals are clocked through the PCI repeater; hence, a one clock delay is built in.
Because of the inherent delay, one of the buses will complete the transaction before the other.
To prevent the earlier finishing bus from starting another transaction while the later finishing bus is completing the transaction, the arbiter removes any pending grants and will not grant the bus to any device on either bus until the later finishing bus has completed the transaction.
This technique works especially well for bursted transactions where the target is unable to move data at the same speed as an initiator.
Upstream transactions are handled like downstream transactions, except if there is a subtractive decode agent on the secondary such as an ISA bus bridge.
Since only one subtractive decode agent can reside on a bus, the transaction is not subtractively decodable both upstream to the primary bus and downstream to the ISA bus.
In a first alternative, subtractive decoding to the ISA bus by a PCI to ISA bridge is disabled if the transaction is initiated on the secondary bus.
This provides peer to peer transactions only between devices on the primary and secondary buses.
In a second method, ISA subtractive decoding is enabled.
After the transaction starts on the secondary bus, the secondary bus clock is halted to allow a target on the primary bus to claim the transaction