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 Convolutional interleaving/de-interleaving method and apparatus for data transmission

Details
Inventors: Ben-Efraim, Nadav; Liu, Peter T.;
Assignee: LSI Logic Corporation (Milpitas, CA)
Primary Examiner: Beausoliel, Jr.; Robert W.
Assistant Examiner: Chung; Phung My
Attorney, Agent or Firm: Poms, Smith, Lande & Rose

In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.

DETAILED DESCRIPTION OF THE INVENTION A convolutional interleaver/de-interleaver apparatus 60 that is constructed and operates in accordance with a method of the present invention is illustrated in FIG.
3.
The apparatus 60 comprises a computer 62, which can be a microprocessor or other suitable computing element.
It is further within the scope of the invention to embody the computer 62 as dedicated hardwired circuitry.
The apparatus 60 further comprises a random access memory (RAM) 64 including a portion 64a for storing data that is being interleaved or de-interleaved.
The memory 64 also stores an operating program and intermediate variables for controlling the operation of the apparatus 60 using the computer 62.
Further illustrated in FIG.
3 is a sequencer logic unit 66 for controlling addressing of the memory 64 and other arithmetic and logical operations under control of the computer 62.
Although the unit 66 is illustrated as being a separate element, it is within the scope of the invention to incorporate the functionality of the unit 66 into the computer 62.
The portion 64b of the memory 64 is also divided into a plurality of segments for storing data symbols or bits that are to be interleaved or de-interleaved.
Where the apparatus 60 is applied for practicing the interleaving/de-interleaving method described in the above-referenced article to Forney, the segments are defined as having different numbers of locations C.
sub.
K respectively, which are defined by the relation C.
sub.
K =K.
times.
.
left brkt-top.
N/B.
right brkt-top.
.
The term .
left brkt-top.
N/B.
right brkt-top.
is the mathematical "ceiling" of the ratio N/B, such that the numerical value of N/B, which does not have to be an integer in accordance with the present invention, is rounded up to the next highest integer value.
For example, if N/B=2.
3, then .
left brkt-top.
N/B.
right brkt-top.
=3.
More specifically, K is a segment number from K.
sub.
0 to K.
sub.
(B-1), C.
sub.
K is the number of memory locations in the segment K, N is a predetermined block length of the symbols and B is a predetermined interleaving depth



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