Data delay circuit and clock extraction circuit using the same

DETAILED DESCRIPTION It is a general object of the present invention to provide a novel and useful data delay circuit in which the aforementioned disadvantages are eliminated.
A more specific object of the present invention is to provide a data delay circuit that is capable of delaying high-speed data by an arbitrary delay of time without causing a deterioration of signal waveform and that is fabricated in the form of IC.
The above objects of the present invention are achieved by a data delay circuit including a first transistor, and a second transistor having a base, an emitter and a collector.
Input data is applied to the bases of the first and second transistors.
A constant-current source is coupled between the emitters of the first and second transistors and a negative power source.
A capacitor is connected between the collector of the first transistor and the collector of the second transistor.
The data delay circuit further includes a third transistor and a fourth transistor.
The emitters of the third and fourth transistors are connected to the collectors of the first and second transistors, respectively.
The bases of the third and fourth transistors are provided with control data having the polarity opposite to that of the input data and having an adjusted amplitude level corresponding to a desired delay time to be given the input data.
First and second load resistors are respectively coupled to the collectors of the third and fourth transistors through a positive power source.
Delayed input data or output data is drawn from the collectors of the third and fourth transistors.
The above-mentioned data delay circuit may be cascaded to obtain a large delay of time.
Another object of the present invention is to provide a clock extraction circuit using the aforementioned data delay circuit.
This object of the present invention is achieved by a timing extraction circuit comprising data delay circuit having an input terminal and an output terminal, and an exclusive-OR gate having a first input terminal to which input data is applied, a second input terminal coupled to the output terminal of the data delay circuit, and an output terminal