Data processor with sets of two registers where both registers receive identical information and when context changes in one register the other register remains unchanged

DETAILED DESCRIPTION In general, one form of the invention is a data processing device including an instruction decoder and an arithmetic logic unit having first and second inputs and an output.
An accumulator is connected between the output and first input of the arithmetic logic unit.
A further register is connected between the accumulator and the second input of the arithmetic logic unit.
The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as well as an additional circuit.
The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command.
Other device, system and method forms of the invention are also disclosed and claimed herein.
Other objects of the invention are disclosed and still other objects will be apparent from the disclosure herein.