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Home Multiplexer-related Data-transfer-control-method-for-controlling-transfer-of-data-through-a-buffer-without-causing-the-buffer-to-become-empty-or-overflow

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Details
Inventors: Kodama, Satoshi; Ogata, Mikito; Kaga, Shigeru; Shiraki, Shinjiro;
Assignee: Hitachi, Ltd. (Tokyo, JP); Hitachi Computer Engineering Co., Ltd. (Kanagawa-ken, JP); Hitachi Computer Peripherals Co., Ltd. (Kanagawa-ken, JP)
Primary Examiner: Ellis; Richard L.
Assistant Examiner:
Attorney, Agent or Firm: Antonelli, Terry, Stout & Kraus, LLP

A data transfer control system in a data transfer apparatus including a plurality of data processing units having different data transfer speeds and a temporary holding circuit provided between the data processing units for temporarily holding data transferred between the data processing units. The data transfer apparatus sends a transfer request for data corresponding to a data storage capacity of the temporary holding circuit of the data transfer apparatus to the data processing unit on the side of sending data and sends a transfer request for data corresponding to the data storage capacity of the temporary holding circuit after an elapse of a delivering time of data to an information processing unit on the data transferred side of the temporary holding circuit from the time of the data transfer request is sent until the requested data from the data processing unit on the data sending side reaches the temporary holding circuit of the data transfer apparatus.

DETAILED DESCRIPTION The reason why the buffer becomes empty is that the next data request to the higher-rank CPU is stopped until data has been received when a request for data transfer to the buffer is sent from the communication control unit to the higher-rank CPU.
The reason why the data request is stopped is to prevent data from overflowing from the buffer (a pointer at an input side is prevented from passing a pointer at an output side).
Accordingly, in order to prevent data from being interrupted in the buffer, while at the same time keeping the data from overflowing from the buffer, when a data request is sent to the higher-rank CPU from the communication control unit, data requests are first sent out in succession based on the buffer capacity and then are sent with an interval corresponding to a delivering time of data for one data request from the buffer to the lower-rank memory unit between the sending of one data request and the sending of the next data request, so that an interval of sending the data requests from the information recording sub-system to the higher-rank CPU is coordinated with the buffer capacity and the sweep-out time for one unit of data from the buffer.
According to the present invention, utilization of a transfer delay time set to the length of the cable for connecting the information recording sub-system and the higher-rank CPU can allow data to be written into the buffer periodically, and, since the buffer does not become empty, a transfer waiting time to the lower-rank memory unit can be eliminated to attain efficient data transfer.



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