Delay line time compression correlation circuit

DETAILED DESCRIPTION OF THE DISCLOSURE FIG.
1 is a schematic representation of a control counter 10 which provides the STATE TIME for the delay line time compression correlation circuit of the disclosed invention.
The control counter 10 is a binary counter wherein the first ten stages are used to provide the STATE TIME.
Specifically, the first five stages Q, through Q.
sub.
5 are used to provide the COUNT STATE outputs A through E; and the next five stages Q.
sub.
6 through Q.
sub.
10 provide the BEAM STATE outputs F through J.
Q.
sub.
1 represents the lowest order, namely 2.
sup.
1, Q.
sub.
2 represents 2.
sup.
2, and so forth.
In the description of FIG.
2 that follows below, inverses of the some of the COUNT STATE and BEAM STATE outputs are utilized.
Such inverses are identified as A, B, and so forth.
Although the control counter 10 does not directly provide such inverse outputs, it is generally known in the art that an inverse signal can be provided by using a logical inverter.
The control counter 10 increments by one on the negative-going transition of the CLK clock signal applied to the CK terminal, as symbolically indicated adjacent the CK terminal.
The control counter 10 is shown as a twelve stage binary counter wherein the two highest order outputs are not utilized for generating STATE TIME.
However, the presence of the unused high order stages does not affect the STATE TIME sequences provided by the COUNT STATE and the BEAM STATE.
An example of a commercially available binary counter that could be used as the control counter 10 is the RCA CD4040A.
Of course, a ten stage binary counter that increments on a clock transition could be used to provide STATE TIME.
The clock signal CLK provided to the control counter 10 is the inverse the common clock signal CLK that is applied to the correlation circuit of FIG.
2, described further below.
Therefore, in the drawing and in the following description, references to the clock signal CLK refer to the same signal, and CLK identifies the inverse of the CLK clock signal