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Details
Inventors: Sonalkar, Ranjan V.; Helms, Howard David;
Assignee: AT&T Corp (New York, NY)
Primary Examiner: Kizou; Hassan
Assistant Examiner: Elallam; Ahmed
Attorney, Agent or Firm:

A digital channelizer employs a polyphase filter element in which a shift register is used to commutate time series data to a bank of polyphase filters at the inputs of an FFT module. The filter bank and FFT module are updated at a frequency that is independent of the rate that the data is fed into the buffer and filter/FFT cycle rates of less than the ratio of the input data rate to the number of input channels may be accommodated by the shift register commutation. The output of the FFT module is interpolation filtered by inserting interpolated points between adjacent data points in the channelized output stream to increase the output frequency by an integral multiple of the update rate of the polyphase filter/FFT update rate. By determining an integer, q, such that (R.sub.o /R.sub.i)(2N-q) is a non-zero integer l, where R.sub.o is a desired output data rate, R.sub.i is an input data rate and 2N is the number of output channels (M<N), updating the filter/FFT at a rate of R.sub.i /(2N-q), and interpolation filtering by inserting l-1 interpolated data between each successive pair of channelized data, a desired output data rate can be matched with an input data rate.

DETAILED DESCRIPTION OF THE EMBODIMENTS Referring to FIG.
5, a polyphase channelizer 200 according to an embodiment of the invention employs a shift register 210 to distribute the time series data over input channels 220 to an FFT block 230 instead of the commutator 141 of the device of FIG.
2.
Referring now also to FIGS.
3 and 4, the contents of filter registers denoted h.
sub.
i (m) and corresponding data registers corresponding to the polyphase system of FIG.
5 are represented as a chart with the condition of the registers at a certain point in time and the condition of the registers after 2N additional points have been sampled.
In a conventional poly-phase application, the data registers would be shifted by exactly the size of the following FFT, that is, by the number of input channels.
Thus, if the FFT has 2N inputs, the 2N data points would be distributed by the shift register and the FFT invoked.
FIG.
3 shows the contents of an example in which the FFT is of size 2N=14 and FIG.
4 shows the contents 2N=14 samples later (equivalent to one sweep of the commutator 141).
Referring to FIG.
6, the spectrum of an example data set with 4 or 6 frequency bands that need to be separated digitally is shown.
The dashed lines show the ideal spectral response of analog band pass filtering typically employed to filter the analog signal prior to digitizing.
The short-long dashed line shows the spectral response of a less ideal BPF with a slower cutoff rate.
Referring again to FIG.
5, a series of polyphase filters h.
sub.
i (m) are employed.
Each filter is formed by taking every 1/2N.
sup.
th point of a low pass filter finite-impulse-response (FIR) that would ordinarily be needed to extract one band of width B from the input data sample at 2NB.
If a P tap FIR is required to meet the channel separation specification, then each of the polyphase filters h.
sub.
i (m) consists of P/2N taps.
Shift register buffer 210 distributes the input data to the 2N digital filters h.
sub.
i (m), one for each input to FFT module



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