Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Multiplexer-related Digital-delay-system-and-method-for-digital-cross-connect-telecommunication-systems

 Phase-locked loop or delay-locked loop circuitry for programmable logic devices
These and other objects of the invention are accomplished in accordance with the principles of the ...


 Parallel data bus integrated clocking and control
A clock is always needed with transmitted data in order to define the position of individual bits ...


 Synchronizing signal detecting circuit
Accordingly, the present invention is directed to a synchronizing signal detecting circuit that ...


 Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
The present invention advantageously addresses the problems above as well as other problems by ...


 Phase detection circuit for stepwise measurement of a phase relation
It is an object of the invention to provide an accurate phase detection circuit comprising few ...


 Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
The present invention is made in view of the aforementioned problems and accordingly an object of ...


 Multiple clock synthesizer
In a preferred embodiment of the invention, there is provided a multiple clock synthesizer having ...


 Phase and frequency adjustable digital phase lock logic system
According to the present invention, a phase lock logic system is provided for determining (i) the ...


 Digital phase alignment and integrated multichannel transceiver employing same
We claim: 1. A synchronizer for phase aligning an input signal, having a data transition, with a ...


 Spread spectrum communication apparatus
It is an object of the invention to rapidly and properly set a transmission power. Another object ...


 Digital delay system and method for digital cross connect telecommunication systems

Details
Inventors: McCallan, Christopher B.;
Assignee: Alcatel Network Systems, Inc. (Richardson, TX)
Primary Examiner: Nguyen; Chau
Assistant Examiner:
Attorney, Agent or Firm: Gray Cary Ware & Freidenrich, LLP

A system and method for provides a generating a plurality of clock phases from a clock signal in a telecommunications cross connect system. The digital delay circuit includes a plurality of delay elements connected in series, each delay element connected to a sampling element, the output of the sampling elements sent to a multiplexor. The total number of delay elements comprises a number that produces a worst case delay equal to or greater than the period of the clock signal. The delay elements receive the rising edge of the clock signal. The delayed rising edges are sent to the sampling elements. The sampling elements send outputs to the multiplexor for determining the number of delay elements transitions by one cycle of the clock signal. A programming device can be coupled to the multiplexor to request from the multiplexor a particular phase of the clock signal. The multiplexor can select the appropriate delay device to generate the particular phase of the clock signal.

DETAILED DESCRIPTION The present invention provides a digital delay system and method for a digital cross connect system that substantially eliminates or reduces disadvantages and problems associated with previously developed delay line systems and methods.
More specifically, the present invention provides a system and method for generating a plurality of clock phases from a clock signal in a telecommunications cross connect system.
The digital delay circuit of the present invention includes a plurality of delay elements, a plurality of sampling elements, and a multiplexor.
The total number of delay elements comprises a number that produces a worst case delay equal to or greater than the period of the clock signal.
The delay elements receive the rising edge of the clock signal.
The delayed rising edges are sent to the sampling elements.
The sampling elements send outputs to the multiplexor to determine the number of delay elements transitioned by one cycle of the clock signal.
In a further aspect of the present invention, a programming device is coupled to the multiplexor to request from the multiplexor a particular phase of the clock signal.
The programming device can receive a request for a particular phase of the clock signal to be generated, divide the number of delay devices transitioned by the binary number representing the requested phase to determine an appropriate delay device at which that phase exists, and instruct the multiplexor to select the appropriate delay device so that the multiplexor generates the requested phase.
The present invention provides an important technical advantage by eliminating the analog delay lines currently used to generate a particular phase of a given clock.
The present invention provides another technical advantage by reducing the cost, complexity, and inaccuracies associated with analog delay lines used in conventional digital cross connect systems to generate a particular phase of a clock.



Related patents
  Apparatus for an improved ISDN terminal adapter having baud rate unblocking and methods for use therein
The present invention overcomes the deficiencies in the art and satisfies this need by providing an ISDN terminal adapter which provides automatic ISDN switch detection, ...
  A/D, D/A Converter for PCM transmission system
It is, therefore, an object of the present invention to provdide a codec which can be commonly adopted in transmission systems which use read/write clocks having a ...
  Start-stop synchronous communication speed detecting apparatus
It is an object of the present invention to provide a start-stop synchronous communication speed detecting apparatus capable of detecting a communication speed without ...
  Modem for connection to a telephone line through a either portable computer connector or a docking station
It is therefore one object of the present invention to provide an improved telephone connection via a modem in a portable (laptop) computer which has a docking station. I...
  Adaptive time division duplexing method and apparatus for dynamic bandwidth allocation within a wireless communication system
The present invention is an adaptive time division duplexing (ATDD) method and apparatus for duplexing transmissions in wireless communication systems. The present ATDD ...
  Fast retrain based on communication profiles for a digital modem
A digital modem that supports fast retrain based on communication profiles according to the present invention includes a memory that stores a plurality of communication ...
  Digital phase locked loop having coarse and fine stepsize variable delay lines
It is therefore an object of the present invention to provide a digital phase locked loop having reduced jitter. According to the present invention, there is provided a ...
  ASIC cell implementation of a bus controller with programmable timing value registers for the apple desktop bus
An ASIC cell implementation of an ADB bus controller for the Apple Desktop Bus has a system interface for connecting to a computer system, and an ADB Interface for ...
  System for initializing a self-timed link
Briefly, the present invention satisfies the need for a way to initialize a self-timed link by providing a protocol that takes into account the unreliable data patterns ...
  System and method for alleviating skew in a bus
The present invention provides a most signal skew tolerant timing window for signal transfer in relation to the capture clock timing. The teaching of this invention is ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved