Digital phase alignment and integrated multichannel transceiver employing same

DETAILED DESCRIPTION We claim: 1.
A synchronizer for phase aligning an input signal, having a data transition, with a reference clock signal, said synchronizer comprising: a delay circuit having an input coupled to receive the input signal, said delay circuit including a plurality of serially connected delay stages, each of said delay stages outputting a correspondingly delayed, input replica as the input signal propagates through said delay circuit; clock adjustment means for receiving the reference clock signal and for producing therefrom a sampling clock signal having a clocking transition, said sampling clock signal having a same frequency as the reference clock signal and a phase offset from the input signal, said phase of the sampling clock signal being offset from the reference clock signal when the reference clock signal is in phase with the input signal; selection means for detecting a phase relationship between said sampling clock signal and at least some of said input replicas, and for identifying based thereon one of said input replicas as synchronized with said sampling clock signal, said identified one of the input replicas comprising a synchronous replica; and output means for retiming and for outputting the synchronous replica as a data output signal phase aligned with the reference clock signal, said output means for retiming the synchronous replica including means for compensating for said clock adjustment means' sampling clock signal phase offset relative to the reference clock signal when the reference clock signal is in phase with the input signal.
2.
The synchronizer of claim 1, wherein said clock adjustment means includes means for initially producing the sampling clock signal to be synchronous with the reference clock signal and for subsequently adjusting the phase of the sampling clock signal relative to the input signal when the reference clock signal is in phase with the input signal such that the clocking transition of the sampling clock signal is phase offset from the data transition of the input signal