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Digital phase locked loop having coarse and fine stepsize variable delay lines
| Details |
Inventors: Saitoh, Tetsuo; Matsuo, Syuji; Taniyoshi, Itsurou; Kitamura, Koichi;
Assignee: NEC Corporation (JP)
Primary Examiner: Chin; Stephen
Assistant Examiner: Kim; Kevim
Attorney, Agent or Firm: Ostrolenk, Faber, Gerb & Soffen, LLP
In a digital phase locked loop, a coarse stepsize variable delay line and a fine stepsize variable delay line are connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits and lower significant bits. The delayed clock pulse is delivered to the input of a clock tree through which the clock pulse propagates and are supplied to various parts of an integrated circuit chip. A phase detector provides a phase comparison between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree. A delay controller counts the reference clock pulse to produce a count value, and increments or decrements the count value in accordance with the output of the phase detector. The up-down count value is supplied as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree. |
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DETAILED DESCRIPTION It is therefore an object of the present invention to provide a digital phase locked loop having reduced jitter.
According to the present invention, there is provided a digital phase locked loop for use with a clock tree having an input and a plurality of clock propagation paths extending from the input to a plurality of outputs.
The digital phase locked loop comprises a coarse stepsize variable delay line and a fine stepsize variable delay line connected in series for receiving a reference clock pulse and imparting thereto variable delays in accordance with higher significant bits applied to the coarse stepsize delay line and in accordance with lower significant bits applied to the fine stepsize delay line, and delivering the delayed clock pulse to the input of the clock tree.
A phase detector provides phase comparison to determine the phase difference between the reference clock pulse and a delayed clock pulse appearing at one of the outputs of the clock tree.
A delay controller is provided, which counts the reference clock pulse to produce a count value.
The controller increments or decrements the count value in accordance with the output of the phase detector and supplies the count value as the higher and lower significant bits to the coarse and fine stepsize variable delay lines at such longer intervals than the intervals at which the reference clock pulse occurs, so that the delayed clock pulse is allowed a sufficient time to propagate through the clock tree.
In the delay controller, a first timing counter is provided for counting the reference clock pulse to produce a count and producing a first timing pulse when the count repeatedly reaches a predetermined value, the first timing pulse defining the start timing of each of the longer intervals.
A sequence controller is responsive to a first occurrence of the first timing pulse for producing a first enable pulse when the output of the phase detector has a first logic level, and responsive to a repeated occurrence of the first timing pulse for producing a second enable pulse when the output of the phase detector has changed to a second logic level
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Multiplexer-related 
