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Details
Inventors: Cotton, John M.; Necula, Nicholas; Parruck, Bidyut; Tyra, Fryderyk; Wissink, Alex T.; Abreu, Enrique;
Assignee: IPC Information Systems, Inc. (Stamford, CT)
Primary Examiner: Chin; Stephen
Assistant Examiner:
Attorney, Agent or Firm: Morgan & Finnegan

A clocking mechanism with improved fault tolerance for synchronizing a distributed processing system includes a plurality of distributed clock sources. Each clock source may operate as a master clock for synchronizing the operations of the entire system or as a slave to an external clock while remaining available, in a backup capacity, to operate as a master clock in the event of a failure in the previous master clock. A clock selection mechanism is provided in each distributed switch element for selecting the best clock available to each switch element for synchronization. A failure recovery mechanism is provided with fast and automatic recovery in the event of a failure in a master clock. A data extraction mechanism is also provided capable of sampling a bit stream that is not phase-aligned, even in the presence of timing jitter and pulse width distortion, and having provisions for detecting a bit slip.

DETAILED DESCRIPTION OF THE DRAWINGS An example of a distributed switching network is illustrated in FIG.
1 for interconnecting various types of voice and data equipment.
The basic building block of the distributed switching network is the switch element.
The switching network is arranged in four stages of switching elements interconnected by a series of communications links, as shown in FIG.
1.
The first two stages, referred to as the interface (I/F) stage 34 and the access switch (AS) stage 36, are in terminal units 38 which provide entry to the switch network for the telephone lines and terminal equipment.
The third and fourth stages referred to as the section switch (SS) stage 40 and the reflection switch (RS) stage 42 are located on switch planes 44.
A more detailed description of the architecture of the switching network is set forth in U.
S.
Pat.
No.
5,255,264 entitled DISTRIBUTED CONTROL SWITCHING NETWORK FOR MULTI-LINE TELEPHONE COMMUNICATIONS (Attorney Docket No.
416-4033).
The disclosure of this application is incorporated herein in its entirety by reference.
A switch element, such as those described in the above-referenced application, is the equivalent of a small intelligent switching matrix.
Each switch element operates independently and is controlled by a separate processor.
In the preferred embodiment, each switch element has nineteen bidirectional switch ports (plus an additional data port).
Each port of a switch element contains 32 separate time-division multiplexed (TDM) channels.
A multiplexed group of 32 channel time slots constitutes a single frame of data and lasts for a duration of 125 microseconds.
Each channel time slot on a communications link constitutes 30 bits of data; therefore, the arriving bit rate is 7.
68 Mbps.
(8000 frames/second.
times.
32 channels/frame.
times.
30 bits/channel).
Furthermore, each channel has a time slot duration of 3.
906 microseconds (125 .
mu.
sec/32).
The processor associated with each switch element controls circuitry which can switch in space (from one port to another) and can switch in time (from one channel to another)



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