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Double buffering operations between the memory bus and the expansion bus of a computer system
| Details |
Inventors: Culley, Paul R.; Taylor, Mark;
Assignee: Compaq Computer Corporation (Houston, TX)
Primary Examiner: Kim; Matthew M.
Assistant Examiner:
Attorney, Agent or Firm: Pravel, Hewitt, Kimball & Krieger
Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG.
1, a computer system C is shown incorporating a double buffering apparatus according to the present invention.
The computer system C is preferably a multiprocessor system, although a computer system according to the present invention may include more processors or may be a single processor system.
The elements of the computer system C that are not significant to the present invention, other than to illustrate an example of a fully configured computer system, are not discussed in detail.
The computer system C preferably includes two CPUs, referred to as CPU 20 and CPU 22, respectively, which are connected to a host bus 24.
The host bus 24 preferably includes a host clock signal referred to as HCLK, which is preferably approximately 25 MHz or 33 MHz depending upon the desired speed of the computer system.
In the preferred embodiment, CPU 20 is logically assigned the position of CPU0, and CPU 22 is assigned logical CPU1, although these assignments are preferably programmable and may be changed.
A memory controller 30 is coupled to the host bus 24 to an expansion bus 42, where the expansion bus 42 is preferably the Extended Industry Standard Architecture (EISA) bus, although other types of expansion buses are contemplated.
The memory controller 30 is also coupled to a main memory array 32, where the memory array 32 preferably comprises dynamic random access memory (DRAM).
A data destination facility (DDF), otherwise known as memory mapper logic 34, is coupled to the memory controller 30 and the memory array 32, and provides memory mapping functions to facilitate memory accesses to the memory array 32.
The memory mapper 34 is used in the preferred embodiment to generate a signal HLOCAL*, which is asserted low when an address appearing on the host bus 24 is to the memory array 32.
An asterisk at the end of a signal name denotes negative logic where the signal is asserted low and negated high.
The computer system C includes an EISA bus controller (EBC) 40, which is coupled between the host bus 24 and the EISA bus 42
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Multiplexer-related 
