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Echo canceller
| Details |
Inventors: Takatori, Hiroshi; Kokumai, Motohiro; Shinozuka, Tatsuko;
Assignee: Hitachi, Ltd. (Tokyo, JP)
Primary Examiner: Ng; Jin F.
Assistant Examiner: Vaas; Randall S.
Attorney, Agent or Firm: Antonelli, Terry & Wands
An echo canceller which cancels an echo by generating a replica of echo from the transmit data when the signal from the transmit line appears as an echo signal on the receive line, and subtracting the replica of echo from the echo signal in a circuit for connecting a transmit line and receive line to the full duplex transmission line through a hybrid circuit. The echo canceller for generating a replica of echo is composed of the first circuit which generates a replica of echo of limited length and a second circuit in which generates a replica of echo for eliminating the residual echo that is not cancelled by the first circuit. |
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DETAILED DESCRIPTION OF THE EMBODIMENTS FIG.
1 is a block diagram illustrating an embodiment of an echo canceller of the present invention.
In FIG.
1, an input terminal 1, encoder 2 and transmitting filter 20 form a transmitting line of a 4-wire system transmission line.
A digital signal which is transmit data of the output of the encoder 2 is transmitted to a 2-wire line 4 for full-duplex transmission through hybrid circuit 3.
A receiving filter 21, adders 14, and 6, line equalizer 7, and decoder 5 are provided in the receive line of the 4-wire system.
The digital data signal transmitted from the 2-wire line 4 is received by the receiving filter 21 through the hybrid circuit 3.
The blocks A and B generate a replica of echo.
The Block A generates a first replica of echo of the limited length, while block B, generates a second replica of echo after the period of the first replica of echo of a limited length.
The block A which generates the first replica of echo has a function similar to that of known table look-up echo canceller and transversal filter, and, directly connects in series a plurality of delay elements each of which has the delay time of a time slot (Baud Rate Timing) (or bit period) of a transmission signal.
The block A generates the first replica of echo from the RAM memory 9 with its tap output used as an address.
For simplification of explanation, the transmitting data is assumed as a single pulse as shown in (a) of FIG.
2.
The echo which flows through the transmitting filter 20, hybrid circuit 3 and receiving filter 21 is indicated as (b).
The first replica of echo generating circuit of block A generates the replica of echo (c) of limited length (time slot 5) and it is subtracted from the echo (b).
Thereby the residual echo (d) is obtained.
In the present invention, the second replica of echo (f) approximated to the residual echo (d) is generated by the second replica of echo generator of block B having a simplified structure.
In this embodiment, the second replica of echo generator is formed by a first order recursive digital filter and receives an input of a signal having a constant limited length obtained by delaying the transmit data by the first replica of echo generator
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Multiplexer-related 
