High speed on-chip clock phase generating system

DETAILED DESCRIPTION It is the principal object of the present invention to provide a novel clock system for a processing system that has a synchronized clock circuit on each logic chip in the processing system.
It is another principal object of the present invention to provide a master clock control circuit for starting, stopping and running on-chip clock phase generators.
It is another principal object of the present invention to provide a master clock controlled circuit for stopping and starting any on-chip clock phase generator at pre-determined clock phase times.
It is another principal object of the present invention to provide a processing system employing a plurality of clock phase generators that do not require field adjustment.
It is another principal object of the present invention to provide a clock phase generating system that requires a minimum number of factory adjustments.
It is another principal object of the present invention to provide a clock system for a processing system that compensates for skew at each logic level down to the on-chip clock generator level.
It is another general object of the present invention to provide on-chip clock generators having interface adaptor circuits for receiving off-chip control signals.
It is another general object of the present invention to provide off-chip control signals to on-chip clock generators that may be stepped or sequenced for test purposes.
It is another general object of the present invention to operate pre-determined on-chip clock generators of a clock generation system in a synchronized step mode or in a synchronized burst mode while operating the processing system in real time.
It is another general object of the present invention to provide a clock generation system having a plurality of clock controlled circuits, one of which is selectable to operate as the master clock control.
It is another general object of the present invention to provide a clock generation system which permits removal and replacement of unit cards while the remainder of the processing system is maintained in a run mode