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Image reject mixer, circuit, and method for image rejection
| Details |
Inventors: Mole, Peter John; Van Vliet, Henric; Babla, Chettan;
Assignee: Nortel Networks Limited (Montreal, CA)
Primary Examiner: Urban; Edward F.
Assistant Examiner: Perez-Gutierrez; Rafael
Attorney, Agent or Firm: Lee, Mann, Smith, McWilliams, Sweeney & Ohlson
To reduce the impact of image frequencies generated by mixing an incident carrier signal down to a relatively low intermediate frequency signal used in subsequent signal processing, a mixing frequency is selected such that the generated intermediate frequency signal has a frequency offset relative to DC that is substantially that of a single channel spacing between frequency adjacent incident carrier signals, as shown in FIG. 2. Image rejection is further improved through the integration of a current-driven polyphase filter (36) directly between an input stage (Q1 to Q4) and a mixer stage (Q5 to Q12) of an image reject mixer (FIG. 4) such as to mitigate quadrature divergence between separate in-phase and quadrature paths within the image reject mixer. |
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DETAILED DESCRIPTION According to a first aspect of the present invention there is provided an integrated image reject mixer circuit responsive to an information-bearing signal and arranged to be coupled to a local oscillator that provides phase-referenced signals thereto and wherein the information-bearing signal has in-phase and quadrature components, the integrated image reject mixer circuit comprising: circuit arrangements of first, second, third and fourth mixer paths each containing: a signal input for receiving the information-bearing signal; a mirrored pair of mixer transistors for receiving selected phase-referenced signals, each mirrored pair of mixer transistors further configured to receive a dedicated phase aligned information-bearing signal for frequency down conversion to a respective intermediate frequency component through mixing with one of the selected phase-referenced signals; and a polyphase filter integrally formed directly between the signal inputs and the mirrored pairs of mixer transistors of each of the first, second, third and fourth mixer paths such that the phase aligned information-bearing signals in each of the respective first, second, third and fourth mixer paths are generated within each mixer path and have a substantially quadrature phase shift therebetween. Preferably, the phase-referenced signal applied to each mirrored pair of mixer transistors has a frequency such that mixing with the information-bearing signal forms an intermediate frequency signal having a frequency offset relative to DC that is in an approximate range of between a half channel spacing and a single channel spacing. Beneficially, integration of the polyphase filter can be achieved with an overall reduction in the number of components in view (particularly) of the elimination of the requirement to provide discrete buffering components and the advantage that the polyphase filter and the image reject mixer can be current driven (without imposing an increased drain on any available power source, such as a battery)
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