 Digital phase locked loop having coarse and fine stepsize variable delay lines |
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| System for initializing a self-timed link |
| Briefly, the present invention satisfies the need for a way to initialize a self-timed link by ... |
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| System and method for alleviating skew in a bus |
| The present invention provides a most signal skew tolerant timing window for signal transfer in ... |
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| Phase-locked loop or delay-locked loop circuitry for programmable logic devices |
| These and other objects of the invention are accomplished in accordance with the principles of the ... |
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| Parallel data bus integrated clocking and control |
| A clock is always needed with transmitted data in order to define the position of individual bits ... |
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| Synchronizing signal detecting circuit |
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| Phase detection circuit for stepwise measurement of a phase relation |
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Integrated processor system adapted for portable personal information devices
| Details |
Inventors: Buxton, Clark L.; Craycraft, Donald G.; Hawkins, Keith G.; Baum, Gary;
Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA)
Primary Examiner: An; Meng-Ai T.
Assistant Examiner: Davis, Jr.; Walter D.
Attorney, Agent or Firm: Conley, Rose & Tayon, Kowert; Robert C., Daffer; Kevin L.
An integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs. The integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality. The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor. The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal. A power management unit is incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions. The pin-count of the integrated processor is finally minimized by allowing the selective multiplexing of certain external pins depending upon the desired functionality of the integrated processor. |
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DETAILED DESCRIPTION The problems outlined above are in large part solved by a highly integrated, low-power integrated processor in accordance with the present invention.
The integrated processor is fabricated on a single monolithic circuit and employs circuitry to accommodate data-intensive, view-intensive and voice-intensive requirements of modern-day PIDs.
Importantly, the integrated processor includes a CPU core, a memory controller, and a variety of peripheral devices to achieve versatility and high performance functionality.
The integrated processor consumes less power by provision of a clock control unit including a plurality of phase-locked loops for generating clock signals of differing frequencies to appropriately clock the various subsystems of the integrated processor.
The clock signals provided to the various subsystems by the clock control unit are derived from a single crystal oscillator input signal.
Since only one external crystal oscillator circuit is required, power consumption is substantially reduced.
A power management unit is further incorporated within the integrated processor to control the frequency and/or application of certain clock signals to the various subsystems, as well as to control other power management related functions.
The pin-count of the integrated processor is finally minimized by allowing the selective multiplexing of certain external pins depending upon the desired functionality of the integrated processor.
In one user-defined mode, the external pins are allocated to an internal video controller, such as a CGA LCD controller.
In another mode, the external pins are allocated to provide an external interface to selected lines of a CPU local bus of the integrated processor.
In yet an additional mode, the external pins are allocated to provide an external interface to selected lines of a peripheral bus, such as an ISA-style bus, of the integrated processor.
Wide versatility of the integrated processor is thereby advantageously achieved while minimizing the overall pin count of the integrated processor
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Multiplexer-related 
