Label-switching and control interface for asynchronous fast-packet switching

DETAILED DESCRIPTION We claim: 1.
A label-switching and control interface for fast packet switching, comprising: a plurality of bidirectional asynchronus multiplex lines forwarding information-signal cells representing respective packets and corresponding to different calls; respective programmed-logic units connected to each of said bidirectional asynchronous multiplex lines for fast cell processing; a multiplex switching network having an input bus connected to all of said programmed-logic units; an arbitrating circuit between said input bus and said multiplex switching network and having a first bus connected therewith, said arbitrating circuit controlling communication between said programmed-logic units selectively and said multiplex switching network; a distribution circuit connected to all of said programmed-logic units by a second bus and to an output bus of said multiplex switching network; a common control circuit connected to all of said programmed-logic units by a third bus and accessing said multiplex switching network through a first connection to said arbitration circuit; and means forming a second connection between said distribution circuit and said control circuit whereby said multiplex switching network accesses said common control circuit.
2.
The label-switching and control interface as defined in claim 1 wherein each of said programmed logic units comprises an incoming section comprising: circuits detecting cell locations in a data flow along said lines; circuits separating datum cells from signalling, supervision, stuffing, auxiliary flow cells, carrying out label switching and adding self-routing code for the multiplex switching network; circuits for controlling the forwarding of cell octets to the multiplex switching network and for the temporary storage of a service class; circuits including a memory for storing cells for multipoint connections and for retransmission of the stored cells for a requested number of times; a further arbitrating circuit among sources of cells to be sent to the switching network; a processor; a temporary memory for cells intended for the processor and an interface for access to the memory by the processor; and an auxiliary output interface for emission of cells of an auxiliary information flow