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Method and apparatus for dispatching multiple interrupt requests simultaneously
| Details |
Inventors: Chou, Hong-Chich; Fan, Jerng-Cherng; Chang, Tsahn-Yih; Kang, Po-Chuan;
Assignee: Industrial Technology Research Institute (Hsinchu, TW)
Primary Examiner: Sheikh; Ayaz R.
Assistant Examiner: Lefkowitz; Sumati
Attorney, Agent or Firm: Proskauer Rose LLP
An interrupt processing method and apparatus particularly well-suited for use in an interrupt controller of a multiprocessor system or device. Each of the interrupt requests has at least one destination processor associated therewith for servicing the interrupt request. An interrupt controller in accordance with the present invention applies latched interrupt requests to a priority compare tree which serves to prioritize received interrupt requests. A number of higher priority requests, including the highest priority request, are supplied to a destination selection circuit which includes an interrupt dispatcher which determines a processor to which the first priority interrupt request will be dispatched. Similar determinations are made for the remaining identified interrupt requests, but with the corresponding destination register contents masked to prevent processors already selected to receive a higher priority interrupt from being considered for a lower priority interrupt. The destination selection circuit attempts to determine a unique destination processor for each of the highest priority interrupt requests, such that these multiple interrupt requests can therefore be dispatched to different processors simultaneously. One or more of the interrupt requests may be "blocked" during a particular time period because all destination processors which could service the blocked requests are already processing other interrupts, performing higher priority tasks or are otherwise unavailable. These blocked interrupt requests are identified and the corresponding destination registers are masked such that the remaining non-blocked interrupt requests can be delivered to an available destination processor. |
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DETAILED DESCRIPTION The present invention provides an improved interrupt processing method and apparatus particularly well-suited for use in a multiprocessor interrupt controller.
The interrupt controller may be configured to dispatch multiple interrupt requests simultaneously.
The interrupt controller may also be configured to select a highest priority non-blocked interrupt request from multiple pending non-blocked interrupt requests, such that when all possible destination processors of the highest priority interrupt request are unavailable, the remaining non-blocked interrupt requests can be selected and dispatched.
One aspect of the invention relates to the simultaneous delivery of multiple interrupt requests in a multiple processor system.
As noted above, conventional interrupt controllers generally dispatch only a single interrupt request at a time, and system performance is therefore limited.
An interrupt controller in accordance with the present invention may include a pending interrupt register which latches interrupt requests received from various external sources.
The outputs of the pending interrupt register are applied to a priority compare tree which includes multiple levels of comparators and serves to prioritize the received interrupt requests.
An exemplary embodiment for use in a system with four processors identifies four higher priority interrupt requests, including the highest priority interrupt request.
These requests are supplied to a destination selection circuit which utilizes destination registers for storing a four-bit indicator for each of the four identified interrupt requests with each bit of the indicator specifying whether or not a particular one of the four processors is a possible destination register for the corresponding interrupt request.
The destination processor information for the first priority interrupt (which is also the highest priority) is applied to a first interrupt dispatcher which determines the processor to which the first priority interrupt request will be dispatched
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