Method and apparatus for operating the internet protocol over a high-speed serial bus

DETAILED DESCRIPTION In accordance with a first aspect of the invention, a method of reconfiguring the bus lint without disturbing the on-going traffic on the bus is provided.
The method includes the step of obtaining the non-changeable address of the component, which does not change during a bus reset, and the changeable address, which is assignable.
The method further includes the step of placing the non-changeable address and changeable address in a look-up table.
In addition, the network is reconfigured.
The method further includes the step of determining the non-changeable address of the component.
The look-up table is examined for the changeable address which corresponds to the non-changeable address.
In addition, the component is assigned the changeable address which was placed in the look-up table prior to bus reset.
In accordance with a second aspect of the invention, a data processing system is provided.
The data processing system includes a bus line and a module connected to the bus line.
The module has a memory which contains a network identifier address.
In addition, the data processing system includes a network manager connected to the bus line.
The network manager has a memory device and a processor with the memory device having a look-up table containing the network identifier address and the changeable address.
The processor has a comparator for comparing the network identifier address in the look-up table with the network identifier address in the module.
In accordance with a third aspect of the invention, a method for determining whether to process an incoming data stream to a component is provided.
The method includes the step of determining the first packet identifier contained in the first memory device of the first component.
The method further includes the step the packet is formed having a field containing the first packet identifier.
In addition, the packet is sent onto the bus.
The method further includes the step of determining by the second component the second packet identifier contained in the second memory device of the second component