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Multiplexer-related

Method-and-apparatus-for-sequencing-two-digital-signals

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Method and apparatus for sequencing two digital signals

Details

Inventors: Geise, Heinz-Dieter; Hoppe, Karl-Heinz;
Assignee: Robert Bosch GmbH (Stuttgart, DE)
Primary Examiner: Safourek; Benedict V.
Assistant Examiner:
Attorney, Agent or Firm: Frishauf, Holtz, Goodman & Woodward

A first self-timing signal bi-phase-mark coded and having a data portion and a synchronization portion is to be sequenced by a second signal also having a data and a synchronization portion. The signals derived by differentiating only the level change at the end of each bit cell phase-lock an oscillator whose output provides the basic timing for a modulator stage. In the modulator stage, a flip-flop first changes state under control of the first signal. At the start of the synchronization portion of the first signal, a comparator furnishes a signal which switches control of the flip-flop to signals derived from differentiation of the second signal. When the second signal is binary coded, a NAND gate modulates the pulses from the second signal by pulses resulting from differentiating negative going edges of the signal derived from the phase-locked oscillator to create a signal for controlling the flip-flop so that it changes state in accordance with a bi-phase-mark code.

DETAILED DESCRIPTION We claim: 1.
Method for creating a sequenced signal by continuing a self-timing first signal having alternate data and synchronization portions with a second signal having alternate data and synchronization portions, said synchronization portions of said second signal having a "1" and a "0" pattern identical to the "1" and "0" pattern of said synchronization portion of said first signal, said first signal being coded so that "1" and "0" bits are represented by changes between a first and second signal level, whereby the initial level of each of said synchronization portions of said first signal varies in dependence upon the signal level at the end of the last previous one of said data portions, the improvement comprising the steps of creating a signal level on a predetermined line (52) corresponding to said signal level at said end of said data portion of said first signal; switching said signal level on said predetermined line in accordance with said "1" and "0" pattern of said synchronization portions of said first and second signals throughout said synchronization portion, said switching being controlled by said second signal after a predetermined time instant in said synchronization portion; and thereafter switching said signal level on said predetermined line in accordance with said second signal, whereby said level changes on said predetermined line constitutes said sequenced signal.
2.
A method as set forth in claim 1, wherein said predetermined time in said synchronization portion is the start of said synchronization portion.
3.
A method as set forth in claim 1, wherein said first signal is a biphase mark coded signal and said second signal is a binary coded signal; further comprising the step of generating timing signals (T.
sub.
0.
degree.
, T.
sub.
90.
degree.
) at time instants corresponding to the end and middle of each of said bits in said first signal; and wherein switching said signal level on said predetermined line under control of said second signal comprises switching said signal level in response to timing signals indicative of said middle of said bit only in the presence of a "1" bit in said second signal and in response to a timing signal signifying said end of said bit in the presence of a "0" bit of said second signal

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