 Input/output cache |
| It is therefore an object of the present invention to provide a system memory to input/output ... |
|
| System and method for transmitting data from a server application to more than one client node |
| The invention relates to a system and method for transmitting the same data to more than one client ... |
|
| Apparatus for delaying and recording time code signals |
| It is an object of the present invention to provide a time code signal recording circuit wherein ... |
|
| High-speed digital PLL device |
| An object of the present invention is to eliminate the above problems, and to provide a high-speed P... |
|
| Magnetic disk storage apparatus with phase sync circuit having controllable response characteristic |
| In recent years, a technique has been proposed to write data with a predetermined constant linear ... |
|
| Method and apparatus for CT image registration |
| OF PREFERRED EMBODIMENTS As a step towards an accurate and clinically applicable registration, the ... |
|
| Synchronization apparatus |
| In accordance with the present invention, there is now provided synchronization apparatus ... |
|
| Phase lock loss detector |
| What is claimed is: 1. A system for detecting phase lock loss between first and second two level ... |
|
| CMOS pseudo-NMOS programmable capacitance time vernier and method of calibration |
| The present invention is directed to a time vernier providing fine timing control of an input ... |
|
| Low power, slew rate insensitive power-on reset circuit |
| The problems outlined above are in large part solved by the power-on reset circuit of the present ... |
|
|
Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
| Details |
Inventors: Davis, Barry R.; Goble, Scott;
Assignee: Intel Corporation (Santa Clara, CA)
Primary Examiner: Shin; Christopher B.
Assistant Examiner:
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
A PCI-to-PCI bridge is described having a processor configured for performing various routing operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are described herein as "programmable decode modes." In one programmable decode mode, private address spaces facilitate communication between peer PCI devices without burdening the primary PCI bus or any upstream components such as a host-to-PCI bridge, a host bus and host microprocessors. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. The transactions are routed to the primary PCI bus. Another programmable decode mode is "intelligent" bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus. Only addresses within programmable reverse positive decode address spaces are captured by the secondary PCI interface and forwarded to the corresponding primary PCI bus. Intelligent bridging allows, among other functions, the interconnection of two peer primary PCI buses by a single PCI-to-PCI bridge. Such enables transactions between PCI devices of the peer PCI buses to be routed over the PCI-to-PCI bridge without requiring routing through a host bus. |
|
DETAILED DESCRIPTION In accordance with one aspect of the invention, error conditions are avoided on a secondary PCI bus employing a private address space by implementing "subtractive transaction routing" within the secondary PCI interface.
With subtractive transaction routing, any transactions on the secondary PCI bus that are not claimed within a predetermined number of clock cycles are automatically captured by the secondary PCI interface and routed to the primary PCI bus.
Hence, any transactions within the private address space which are not properly captured by one of the devices connected to the secondary PCI bus are ultimately captured by the secondary PCI interface, thereby avoiding error conditions.
The subtractive operation is, however, not limited to transactions within the private address space but applies to any transactions within the PCI address space not captured within the predetermined number of clock cycles.
In accordance with another aspect of the invention, an improved PCI bus system is provided which facilitates transmission of transactions between PCI devices connected to peer PCI buses.
The improved PCI bus system includes a pair of peer primary PCI buses interconnected through respective host-to-PCI bridges to a host bus which interconnects one or more host microprocessors.
A single PCI-to-PCI bridge interconnects the pair of peer primary PCI buses.
With this arrangement, transactions generated by a PCI device connected to one of the primary PCI buses may be routed through the PCI-to-PCI bridge to a device connected to the other PCI bus.
In other words, the host bus and the host-to-PCI bridges are bypassed.
Other more elaborate PCI bus interconnection systems are also feasible.
In one system, three peer primary buses are respectively connected through separate host-to-PCI bridges to a single host bus.
A pair of PCI-to-PCI bridges interconnect the three peer PCI buses.
More specifically, a first PCI-to-PCI bridge interconnects first and second primary PCI buses and a second PCI-to-PCI bridge interconnects second and third PCI buses
|
| Related patents |
|
|
Method and apparatus for dispatching multiple interrupt requests simultaneously
The present invention provides an improved interrupt processing method and apparatus particularly well-suited for use in a multiprocessor interrupt controller. The ...
|
|
|
Apparatus for and method of communicating among devices interconnected on a bus
In view of the above identified limitations of the related art, it is an object of the invention to provide efficient communication among devices communicatively linked ...
|
|
|
Obstacle detecting apparatus using ultrasonic waves
Accordingly, it is the primary object of this invention to provide an obstacle detecting apparatus using ultrasonic waves, wherein an ultrasonic transmitter-receiver and ...
|
|
|
Ultrasonic sensor system
OF THE INVENTION Referring to FIGS. 1 and 2, a doorway is shown in a wall W, the doorway including conventional framing, typically metal for commercial door fronts, ...
|
|
|
Flash analog-to-digital converter with logarithmic/linear threshold voltages
What is claimed: 1. In combination, a member provided with an electrically resistive material on one surface of the member, the member being defined by first and second ...
|
|
|
Traffic information radio signal receiver
I claim: 1. In a radio receiver having a radio signal receiving stage (10) providing program signals and traffic information signals, an audio stage providing audio ...
|
|
|
Method for dynamically allocating wireless communication resources
We claim: 1. In a TDM wireless communication system that includes a plurality of communication units, a plurality of wireless communication resources, and a central ...
|
|
|
Scheduling mechanism for network adapter to minimize latency and guarantee background processing time
The present invention resides in a network adapter scheduling method, and corresponding apparatus, in which a polling loop includes receive data processing, and checking ...
|
|
|
System for transferring portion of data to host from buffer if size of packet is greater than first threshold value but less than second threshold value
OF THE PREFERRED EMBODIMENT A method and apparatus for optimization of buffer memory management in a communications resource is described. In the following description, ...
|
|
|
Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache
Referring now to FIG. 1, there is shown a block diagram of a preferred embodiment of the programmable instruction cache in accordance with the present invention. The ...
|
|
|
Multiplexer-related 
