Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit

DETAILED DESCRIPTION The present invention advantageously addresses the problems above as well as other problems by providing a balanced clock placement method that minimizes clock skew.
In one embodiment, the present invention may be characterized as a method of clock buffer placement for minimizing clock skew that includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.