Method of and circuit arrangement for digitally transferring bit sequences in selective manner

DETAILED DESCRIPTION The invention to this end makes available a method and a circuit arrangement, which can be developed in advantageous manner in accordance with the description herein.
In addition thereto, a test bit generator is provided, which is of significance both for the method and for the circuit arrangement.
The method provides a bus protocol for digitally transferring bit sequences in selective manner between a master means and several selectively controllable slave means via an interface means provided therebetween, making use of bit sequences of predetermined maximum frame length, comprising an address field addressing the respective slave means to be controlled, a control field containing control information, and a data field.
While the address field and the control field each have a predetermined field length or bit number, the data field for the slave means may have different field lengths or data bit numbers as long as the data field does not exceed a (freely selectable) maximum data bit number.
The bit sequences transferred in serial form are written in succession to successive register stages of an interface register and read back to the master means.
Reading back is carried out register stage for register stage immediately after having been written to the respective register stage where writing to a register stage and reading back from this register stage take place during the same clock pulse.
The master means compares the bit read-back from the respective register stage with the bit transmitted for this register stage.
When the read-back memory contents of any of the register stages are not in conformity with the bit transmitted from the master means for this register stage, the master means blocks the transfer of the respective transmitted bit sequence to the respective addressed slave means.
This method ensures that a bit read incorrectly to the interface register is immediately recognized as incorrect, and that clock errors, for example the omission of one or more clock pulses, are recognized