 Echo canceller |
| OF THE EMBODIMENTS FIG. 1 is a block diagram illustrating an embodiment of an echo canceller of ... |
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| Listener echo cancellation |
| The listener echo cancellation means of the present invention employs a finite impulse response (FIR... |
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| Semiconductor integrated device |
| In the integrated service digital network, the training mode for getting the echo data is carried ... |
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| RF power amplifier linearization |
| OF THE PREFERRED EMBODIMENT Referring now to the drawing, schematically depicted in FIG. 1 is an ... |
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| Waste energy control and management in power amplifier |
| OF THE DRAWINGS These and other features and advantages of the invention will be readily apparent ... |
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| Facility for combining and amplifying two broadband signals |
| It is therefore an object of the invention to provide a facility which is suitable for combining ... |
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| Electronic musical instrument for conducting an arpeggio performance of a stringed instrument |
| In view of the foregoing, it is therefore an object of the present invention to provide an ... |
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| Digital automatic gain control, as for a receiver |
| What is claimed is: 1. A gain control for a gain-controllable circuit comprising: means for ... |
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| Method for interconnecting CMOS chip types |
| I have provided a variable voltage driver circuit that is located off chip that produces a variable ... |
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Method of and system for synchronizing data reception and retransmission aboard communication satellite
| Details |
Inventors: Cordaro, Giovanni; Dall'Olio, Cristiano; Di Pino, Duccio; Guarene, Eugenio;
Assignee: CSELT-Centro Studi e Laboratori Telecomunicazioni S.p.A. (Turin, IT)
Primary Examiner: Olms; Douglas W.
Assistant Examiner:
Attorney, Agent or Firm: Ross; Karl F.
A receiver aboard a communication satellite, designed to detect digital signals arriving in intermittent bursts from a ground station with a bit cadence differing but slightly from a clock frequency f.sub.s generated by a time base on the satellite, comprises a synchronizer controlled by that time base for reorganizing the detected bits into a data frame in step with clock frequency f.sub.s preparatorily to processing and retransmission thereof. The synchronizer samples a square wave of frequency 2f.sub.s substantially at the midpoint of an initial bit period of an incoming signal stream, with the aid of a timing signal extracted from that signal stream, and determines from the sample whether this square wave or an inversion thereof is to be used in establishing the instants of reading of the subsequently received bits. The bits thus read, after interim storage in two cascaded registers, are fed to a data processor in the rhythm of clock frequency f.sub.s. No data are lost as long as the drift between the clock cycles and bit periods does not exceed one fourth of a clock cycle for the duration of a burst. |
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DETAILED DESCRIPTION We claim: 1.
A method of timing the reading of data bits in a stream of digital signals intermittently received by a relay station from a remote transmitting station, said digital signals arriving with a bit cadence f.
sub.
g close to a clock frequency f.
sub.
s available at said relay station, comprising the steps of: (a) generating a square wave of frequency 2f.
sub.
s ; (b) extracting a timing signal corresponding to said bit cadence f.
sub.
g from a signal stream of limited duration detected at said relay station; (c) sampling said square wave, in response to said timing signal, at an instant substantially coinciding with the midpoint of an initial bit period of the detected signal stream, said bit period having a length 1/f.
sub.
g approximately equaling a clock cycle 1/f.
sub.
s ; (d) selecting, on the basis of the sample obtained in step (c), one of two mutually interleaved trains of synchronizing pulses each having a cadence corresponding to said clock frequency f.
sub.
s, the first synchronizing pulse so selected occurring in one of the two middle quarters of a bit period; (e) reading the bits of the detected signal stream at the instants of occurrence of the synchronizing pulses of the selected train; and (f) organizing the bits to read into a data frame in step with said clock frequency f.
sub.
s.
2.
A method as defined in claim 1 wherein said interleaved trains of synchronizing pulses are homologous pulse flanks of said square wave and of another square wave of the same frequency 2f.
sub.
s in phase opposition therewith.
3.
A method as defined in claim 1 or 2 wherein the bits read in step (e) are stored to the end of a clock cycle before transfer to a processor as part of the data frame of step (f).
4.
A system for timing the reading of data bits in a stream of digital signals intermittently received by a relay station from a remote transmitting station, comprising: a time base establishing a clock frequency f.
sub.
s close to the bit cadence f.
sub.
g in an incoming stream of digital signals, said time base generating a square wave of frequency 2f
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Multiplexer-related 
