Home | Links | Contact Us | More About Intellectual Property | Bookmark
Search patents:
Home Multiplexer-related Method-of-synchronization-status-message-processing-in-transmission-apparatus

 ASIC cell implementation of a bus controller with programmable timing value registers for the apple desktop bus
An ASIC cell implementation of an ADB bus controller for the Apple Desktop Bus has a system ...


 System for initializing a self-timed link
Briefly, the present invention satisfies the need for a way to initialize a self-timed link by ...


 System and method for alleviating skew in a bus
The present invention provides a most signal skew tolerant timing window for signal transfer in ...


 Phase-locked loop or delay-locked loop circuitry for programmable logic devices
These and other objects of the invention are accomplished in accordance with the principles of the ...


 Parallel data bus integrated clocking and control
A clock is always needed with transmitted data in order to define the position of individual bits ...


 Synchronizing signal detecting circuit
Accordingly, the present invention is directed to a synchronizing signal detecting circuit that ...


 Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
The present invention advantageously addresses the problems above as well as other problems by ...


 Phase detection circuit for stepwise measurement of a phase relation
It is an object of the invention to provide an accurate phase detection circuit comprising few ...


 Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock
The present invention is made in view of the aforementioned problems and accordingly an object of ...


 Multiple clock synthesizer
In a preferred embodiment of the invention, there is provided a multiple clock synthesizer having ...


 Method of synchronization status message processing in transmission apparatus

Details
Inventors: Meki, Seiji; Yamada, Shunji; Moriyama, Junichi;
Assignee: Fujitsu Limited (Kanagawa, JP)
Primary Examiner: Ngo; Ricky
Assistant Examiner:
Attorney, Agent or Firm: Helfgott & Karas, P.C.

A transmission apparatus has units to which main signals are input for subjecting these main signals to predetermined processing and then transmitting them. One of these units is a master unit and the others are slave units and they are interconnected by a clock cable and processor-to-processor cable. Each slave unit detects a synchronization status message that has been inserted into a main signal input from a line and notifies the main unit of this synchronization status message via the processor-to-processor cable. Using synchronization status messages acquired from the slave units and a synchronization status message that has been inserted into a main signal input thereto, the main unit obtains the synchronization status message indicative of the best quality level and adopts, as a master clock, a clock extracted from the main signal into which this synchronization status message has been inserted.

DETAILED DESCRIPTION Accordingly, an object of the present invention is to lighten the load on the master shelf by dispersing the synchronization status message detection processing among the shelves (the master shelf and slave shelves).
Another object of the present invention is to lighten the load on the shelves, especially the master shelf, by sending and receiving synchronization status messages indicating quality via a processor interconnecting cable between the master shelf and slave shelves only when the quality of a clock changes or only when the quality of the master clock changes, and refraining from sending and receiving synchronization status messages if there is no change in quality.
Another object of the present invention is to prevent loss of synchronization in a network by so arranging it that another transmission apparatus will not use a master clock even if the unit of the master that decides the master clock malfunctions.
A further object of the present invention is to prevent loss of synchronization in a network by so arranging it that another transmission apparatus will not use a clock, which is contained in a main signal sent from a slave shelf, even if the unit of the master shelf that selects and processes the master clock sent from the master shelf malfunctions.
Still another object of the present invention is to set synchronization status messages, which indicate the qualities of the clocks, in the overhead S1 bytes of main signals sent from slave shelves even in a case where the cable for sending the master clock is severed and slave shelves use the HO clock or INT clock as the reference clock.
Yet another object of the present invention is to prevent unnecessary changeover of clocks within a network, as well as loss of synchronization in the network, by so arranging it that even when a self-timing clock such as the HO clock or INT clock is being used as a reference clock during the execution of processing to decide the master clock, a synchronization status message indicating the quality of this clock is not transmitted



Related patents
  Docking station
What is claimed is: 1. A docking station, comprising: a platform; a motion control mechanism operably coupled to said platform; a power source operably coupled to said ...
  Network clock synchronization
According to the present invention, there is provided a network comprising an exchange having a masterclock and a number of subscriber stations connected to the exchange ...
  Digital delay system and method for digital cross connect telecommunication systems
The present invention provides a digital delay system and method for a digital cross connect system that substantially eliminates or reduces disadvantages and problems ...
  Apparatus for an improved ISDN terminal adapter having baud rate unblocking and methods for use therein
The present invention overcomes the deficiencies in the art and satisfies this need by providing an ISDN terminal adapter which provides automatic ISDN switch detection, ...
  A/D, D/A Converter for PCM transmission system
It is, therefore, an object of the present invention to provdide a codec which can be commonly adopted in transmission systems which use read/write clocks having a ...
  Start-stop synchronous communication speed detecting apparatus
It is an object of the present invention to provide a start-stop synchronous communication speed detecting apparatus capable of detecting a communication speed without ...
  Modem for connection to a telephone line through a either portable computer connector or a docking station
It is therefore one object of the present invention to provide an improved telephone connection via a modem in a portable (laptop) computer which has a docking station. I...
  Adaptive time division duplexing method and apparatus for dynamic bandwidth allocation within a wireless communication system
The present invention is an adaptive time division duplexing (ATDD) method and apparatus for duplexing transmissions in wireless communication systems. The present ATDD ...
  Fast retrain based on communication profiles for a digital modem
A digital modem that supports fast retrain based on communication profiles according to the present invention includes a memory that stores a plurality of communication ...
  Digital phase locked loop having coarse and fine stepsize variable delay lines
It is therefore an object of the present invention to provide a digital phase locked loop having reduced jitter. According to the present invention, there is provided a ...

0.014

Archive: All patents - Links

Copyright (c)2006 Eipa-patents.org - All rights reserved