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 Methods and apparatus for charging a sense amplifier

Details
Inventors: Liu, Lawrence; Murray, Michael; Li, Li-Chun;
Assignee: Mosel Vitelic (San Jose, CA)
Primary Examiner: Tran; Toan
Assistant Examiner:
Attorney, Agent or Firm: Skjerven, Morrill, MacPherson, Franklin & Friel, Shenker; Michael

A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

DETAILED DESCRIPTION We claim: 1.
A circuit comprising: a sense amplifier having a node for receiving power; and a first circuit for supplying power to the node, wherein during amplification the first circuit is to supply power first from a first voltage, and then from a second voltage which is lower in magnitude than the first voltage, wherein a time that the first circuit is to supply power to the node from the first voltage depends inversely on the magnitude of the first voltage.
2.
The circuit of claim 1 wherein: the sense amplifier comprises an output node; and the first circuit is to supply power to the node from the first voltage until an output signal on the output node reaches an output level, and the first circuit is to supply power to the node from the second voltage but not from the first voltage to keep the output signal at the output level.
3.
The circuit of claim 1 further comprising a timer for defining the time that the first circuit is to supply power to the node from the first voltage, the timer comprising: a first transistor for connecting a node of the timer to a voltage; and an inverter connected between the node of the timer and an output of the timer.
4.
The circuit of claim 3 wherein the timer further comprises a second transistor for connecting the node of the timer to a reference voltage to precharge the node of the timer to the reference voltage; and wherein the first transistor is to turn on and the second transistor is to turn off when the first circuit is to start supplying power from the first voltage, and wherein the first circuit is to stop supplying power from the first voltage and to start supplying power from the second voltage when the node of the timer reaches a trip point of the inverter.
5.
The circuit of claim 3 wherein the first transistor is for connecting the node of the timer to the first voltage.
6.
The circuit of claim 3 wherein the first transistor is a field effect transistor, and the circuit further comprises a circuit for generating a constant voltage on a gate of the first transistor



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