Mobile radio communications system

DETAILED DESCRIPTION This invention is a mobile radio communications system which has radio base stations that are connected to mobile stations by radio channels, and a mobile switching center which is connected to these radio base stations by wire circuits, and wherein this mobile switching center and the radio base stations have means which transmit and receive fixed-length packets through these wire circuits.
The transmitting and receiving means have (i) a plurality of means to which are input low bit-rate digital information signals that have been low bit-rate encoded by techniques such as adaptive differential pulse code modulation, adaptive predictive coding, adaptive transform coding, and adaptive predictive coding with adaptive bit-allocation, and which assemble short packets; and (ii) a plurality of means to which short packets are input, and which disassemble these into low bit-rate digital information signals; where the plurality of means (i) and (ii) are respectively provided in parallel in correspondence with the information signal channels.
The fixed-length packets have a signal length which accommodates a plurality of these short packets.
The transmitting and receiving means also have (iii) means which accommodate the short packets that are output from the assembling means in the fixed-length packets in positions corresponding to the channels, and which transmit these to the wire circuits; and (iv) means which extract and disassemble the packets accommodated in channel-corresponding positions in the fixed-length packets which arrive from these wire circuits, and which transfer them to channels corresponding to the positions in which they were accommodated.
The device corresponding to the transmitting and receiving means on the mobile switching center side can also comprise a first fixed-length packet switch (108) which is provided between the wire circuits (106) and the fixed-length packet assembly/disassembly circuits (114); and a second fixed-length packet switch (133) which is provided between these fixed-length packet assembly/disassembly circuits (114) and the information data assembly/disassembly circuits (113)