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Adaptive time division duplexing method and apparatus for dynamic bandwidth allocation within a wireless communication system
The present invention is an adaptive time division duplexing (ATDD) method and apparatus for duplexing transmissions in wireless communication systems. The present ATDD ...
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Fast retrain based on communication profiles for a digital modem
A digital modem that supports fast retrain based on communication profiles according to the present invention includes a memory that stores a plurality of communication ...
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Digital phase locked loop having coarse and fine stepsize variable delay lines
It is therefore an object of the present invention to provide a digital phase locked loop having reduced jitter. According to the present invention, there is provided a ...
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ASIC cell implementation of a bus controller with programmable timing value registers for the apple desktop bus
An ASIC cell implementation of an ADB bus controller for the Apple Desktop Bus has a system interface for connecting to a computer system, and an ADB Interface for ...
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System for initializing a self-timed link
Briefly, the present invention satisfies the need for a way to initialize a self-timed link by providing a protocol that takes into account the unreliable data patterns ...
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System and method for alleviating skew in a bus
The present invention provides a most signal skew tolerant timing window for signal transfer in relation to the capture clock timing. The teaching of this invention is ...
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Phase-locked loop or delay-locked loop circuitry for programmable logic devices
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing PLL or DLL circuitry on a programmable logic ...
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Parallel data bus integrated clocking and control
A clock is always needed with transmitted data in order to define the position of individual bits in the data sequences. If the clock is directly transmitted, such a ...
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Synchronizing signal detecting circuit
Accordingly, the present invention is directed to a synchronizing signal detecting circuit that substantially obviates one or more of the problems due to limitations and ...
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Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
The present invention advantageously addresses the problems above as well as other problems by providing a balanced clock placement method that minimizes clock skew. In ...
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