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 Motion estimation

Details
Inventors: Sivan, Zohar;
Assignee: International Business Machines Corp. (Armonk, NY)
Primary Examiner: Rao; Andy
Assistant Examiner:
Attorney, Agent or Firm: Darby & Darby

A method of comparing a current block in a current frame to a plurality of background blocks in a preceding frame. Each block includes a matrix of data values arranged in a given number of columns. The method uses a processor which has a plurality of computational registers, each register capable of receiving a number of the data values at least equal to the given number. The data values are loaded from a memory beginning at an address in the memory evenly divisible by the given number. The method includes storing the preceding frame in the memory beginning at an address that is divisible by the given number with a predetermined remainder, loading at least some of the data values of the current block into one or more of the plurality of registers, loading at least some of the data values of one or more of the background blocks into another one or more of the plurality of registers, and comparing the background blocks to the current block using the registers.

DETAILED DESCRIPTION It is an object of some aspects of the present invention to provide methods for fast block comparison using SIMD units.
It is another object of some aspects of the present invention to provide methods for block comparison which require a reduced number of memory accesses.
It is another object of some aspects of the present invention to provide methods for reducing the percentage of time spent on memory access in motion estimation.
In preferred embodiments of the present invention, a processor and a plurality of SIMD registers which are preferably included in the processor, are used for motion estimation of a block in a current frame.
The block in the current frame is compared to a plurality of background blocks in a preceding frame, and the block in the preceding frame most closely resembling the block in the current frame (hereinafter referred to as the current block) is chosen.
The processor is capable of reading into each of the registers a word of 16 bytes beginning at an address in a main memory which is aligned to the size of the registers, i.
e.
, which is an integral multiple of 16 bytes.
In order to facilitate efficient loading of the blocks of the preceding frame into the registers, the preceding frame is loaded into the main memory in a predetermined known alignment.
Although in the predetermined alignment the beginning address may be aligned with the 16-byte registers, preferably the beginning address is deliberately out of alignment with the 16-byte registers.
When loading into the registers a desired word which is not precisely aligned in the memory or whose alignment is not known, two load commands are required to load two 16-byte aligned words that include all the bytes of the desired word.
In addition, a permute command is required to bring the desired word into a single register.
The use of the predetermined alignment, in accordance with the principles of the present invention, allows the use of a relatively fast shift command instead of the slower permute command, since the amount of shift required is known from the predetermined alignment



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