Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof

DETAILED DESCRIPTION To address the above-discussed deficiencies of the prior art, the present invention provides a multi-channel serdes receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver.
In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.
The present invention therefore introduces a multi-channel serdes receiver built around a central frequency synthesizer (clock) and distributed clock and data recovery in each channel-specific receiver.
The clock and data recovery circuit in each channel-specific receiver tracks the frequency offset between the incoming data's clock and the clock generated by the central frequency synthesizer ("PLL").
The multi-channel serdes receiver presented here is capable of tolerating frequency offset between a plurality of channels.
Centralizing the clock reduces interference that occurs when multiple frequency synthesizers run proximate one another and reduces power consumption and concomitant heat generation, which is particularly important when the serdes receiver is embodied as an integrated circuit.
In one embodiment of the present invention, the central frequency synthesizer includes a voltage-controlled oscillator.
Those skilled in the pertinent art will understand that other types of frequency synthesizers are within the broad scope of the present invention.
In one embodiment of the present invention, the central frequency synthesizer is a phase-locked loop (PLL).
The phase-locked loop, while not essential to the present invention, improves the stability and reliability of the central frequency synthesizer.
In one embodiment of the present invention, the plurality further includes at least one integrator coupled to the phase interpolator and a demultiplexer