 Method and system for fast access to an uplink channel in a mobile communications network |
| The present invention comprises a method and system for obtaining fast access to a multiplexed ... |
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| Triple orthogonally interleaed error correction system |
| In accordance with the present invention there is provided a triple orthogonally interleaved error ... |
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| Diversity transmitter/receiver |
| The object of the present invention is to provide a spread-spectrum diversity transmitter/receiver ... |
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| Interleaver and deinterleaver for use in a diversity transmission communication system |
| The current invention enhances the performance of a system utilizing interleaving and transmit ... |
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| System and method for providing packet-switched telephony |
| It is therefore one object of the present invention to provide a method and system for replacing a ... |
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| Two phase local mobility scheme for wireless access to packet based networks |
| Local mobility within a subnet is supported by classifying wireless base stations, and the routers ... |
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| Mobility management in wireless internet protocol networks |
| In a wireless cellular communications network based on the Internet Protocol (IP) where packets to ... |
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| Simple multicast extension for mobile IP SMM |
| In a preferred embodiment, the invention is a method and apparatus for routing data to a mobile ... |
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| Task-driven distributed multimedia consumer system |
| To this end, the invention provides a control system comprising multiple electronic devices ... |
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| Method and apparatus for operating the internet protocol over a high-speed serial bus |
| In accordance with a first aspect of the invention, a method of reconfiguring the bus lint without ... |
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Multi-functional I/O buffers in a field programmable gate array (FPGA)
| Details |
Inventors: Andrews, William B.; Scholz, Harold N.;
Assignee: Lattice Semiconductor Corporation (Hillsboro, OR)
Primary Examiner: Le; Don Phu
Assistant Examiner:
Attorney, Agent or Firm:
A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g., a single ended receiver or transmitter, a reference receiver or transmitter, or a differential receiver or transmitter. The pad logic of the multi-functional I/O buffer may include a double data rate input and output mode, each of which includes two flip-flop devices operating on opposite sides of a data clock signal. One of the two flip-flop devices may be borrowed from another logic element, e.g., from a shift register logic element. |
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DETAILED DESCRIPTION In accordance with the principles of the present invention, a multi-function I/O buffer in a programmable device comprises an enablable differential receiver, and an embedded differential resistance on a same integrated circuit as the enablable differential receiver.
A method of providing multi-functionality in an I/O buffer of a programmable device in accordance with another aspect of the present invention comprises programmably enabling either a differential receiver or a single ended receiver.
A differential transmitter or a single ended transmitter is programmably enabled.
If the differential receiver is enabled, an embedded resistance between input terminals of the differential receiver is also programmably enabled.
If the single ended receiver is enabled, the embedded resistance is programmably disabled.
In yet another aspect of the present invention, an I/O bank in a programmable device comprises a plurality of groups of I/O buffers, each of the I/O buffers being bonded to an external pin for power input.
Each of the I/O buffers is capable of being powered at a different voltage level.
In accordance with still another aspect, an I/O element of a programmable logic device relating to a single external pin of the programmable logic device comprises at least two input flipflop devices.
A first one of the two input flip-flop devices is clocked on a first edge of a clock signal, and the other input flip-flop device is clocked on a second edge of the clock signal, the second edge being opposite the first edge.
Still another aspect includes an I/O element of a programmable logic device relating to a single external pin of the programmable logic device comprising at least two output flip-flop devices.
A first one of the two output flip-flop devices is clocked on a first edge of a clock signal.
A second one of the two output flip-flop devices is clocked on a second edge of the clock signal, the second edge being opposite the first edge.
A method of providing a double data rate mode in a programmable logic device in accordance with an aspect of the invention comprises configuring a first flip-flop to input a data signal clocked on a first edge of a clock signal
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Multiplexer-related 
